Synchronous Timing - Infineon Technologies TC1728 User Manual

17.1.4.3 Synchronous Timing

Figure 17-7 shows timing diagrams of the ASC Synchronous Mode data reception and
data transmission. In idle state, the shift clock is at high level. With the beginning of a
synchronous transmission of a data byte, the data is shifted out at RXD with the falling
edge of the shift clock. If a data byte is received through RXD, data is latched with the
rising edge of the shift clock.
One shift clock cycle (
data bytes.
Receive/Transmit Timing
Shift Clock
(TXD)
Transmit Data
Data Bit n
(RXD)
Receive Data
Valid
(RXD) Data n
Continuous Transmit Timing
Shift Clock
(TXD)
Transmit Data
(RXD)
Receive Data
(RXD)
Figure 17-7 ASC Synchronous Mode Waveforms
User's Manual
ASC, V1.3 2007-11
Asynchronous/Synchronous Serial Interface (ASC)
f
) delay is inserted between two consecutive receive or transmit
BR
Shift Latch Shift Latch Shift
Data Bit n+1 Data Bit n+2
Valid Valid
Data n+1 Data n+2
D0 D1 D2 D3
1. Byte
D0 D1 D2 D3
D4 D5 D6 D7
D4 D5 D6 D7
1. Byte
17-11
TC1728
D0 D1 D2 D3
2. Byte
D0 D1 D2 D3
2. Byte
MCT06206
V1.0, 2011-12