Infineon Technologies C166S V2 User Manual

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Use r Ma nual, V 1.7, Ja nuary 2001

C166S V2

1 6 - B i t M ic r o c o n t r o l l e r

M i c r o c o n t ro l le r s

N e v e r

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t h i n k i n g .

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Page 1 Use r Ma nual, V 1.7, Ja nuary 2001 C166S V2 1 6 - B i t M ic r o c o n t r o l l e r M i c r o c o n t ro l le r s...
Page 2 Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life.
Page 3 Use r Ma nual, V 1.7, Ja nuary 2001 C 1 6 6 S V2 1 6-B it M icr o c ontr ol ler M i c r o c o n t ro l le r s N e v e r s t o p t h i n k i n g .
Page 4 C166S V2 Revision History: 2001-01 V 1.7 Previous Version: Page Subjects (major changes since last revision) We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document.
Page 5: Table Of Contents
Addressing via Data Page Pointer DPP ..... . 49 2.5.2.2 DPP Override Mechanism in the C166S V2 CPU ....51 2.5.2.3 Long Addressing Mode .
Page 6 Dedicated CSFRs ......... . . 89 C166S V2 Memory Organization ....... 91 Data Organization in Memory .
Page 7 User Manual C166S V2 Interrupt System and Control ........118 5.1.1...
Page 8 User Manual C166S V2 Multi Master Systems ........169 6.4.1...
Page 9: Introduction
C166S V2 Introduction Introduction C166S V2 is a member of the most recent generation of the popular C166 microcontroller cores. C166S V2 combines high performance with enhanced modular architecture. It was developed to provide easy migration from standard existing C16x to the new C166S V2 core with its impressive DSP performance and advanced interrupt handling.
Page 10: System Description
• System Control Unit (SCU) Generation Unit (CGU) • Clock The powerful C166S V2 core, the peripherals, and the internal memories of the C166S V2 microcontroller are connected to various busses: • 16-bit high performance system bus • 16-bit enhanced peripheral bus (PDBUS+) •...
Page 11: Cpu
User Manual C166S V2 Introduction Figure 1-1 shows a typical configuration of a C166S V2-based system. C166S V2 MegaCore Data Memory up tp 3 kBytes up tp 24 kBytes C166S V2 CPU DPRAM SRAM Program Memory up to 4MBytes Break...
Page 12: On-Chip Memory Modules
PDBUS+) and instruction fetches in external memory. The DMU acts as a data mover between the various interfaces. By handling all these interfaces, it incorporates the C166S V2 System Bus. An access prioritization between External BUS Controller (EBC) accesses from the core Program Memory Unit ( PMU) is handled by the DMU.
Page 13: Interrupt And Pec Controller
– Interrupt servicing during break or monitor mode – Simple monitor mode or JTAG based debugging through instruction injection The C166S V2 OCDS is controlled by the debugger through a set of registers accessible from the JTAG interface. The OCDS also receives informations (such as IP, data, status) from the core for monitoring the activity and generating triggers.
Page 14: Clock Generation Unit (Cgu)
The C166S V2 System provides asynchronous fast external interrupt inputs. Central System Control The central system behavior of the C166S V2 is controlled by this block. The frequency of the PDBUS+ (bus clock) and of all peripherals connected to this bus is programmable according to the maximum physical bus speed and the application requirements.
Page 15: Central Processing Unit
Central Processing Unit Central Processing Unit C166S V2 CPU represents the third generation of the well known C166 core family. It combines many powerful enhancements with compatibility to the C166 family. The new architecture results in high CPU performance, fast and efficient access to different kinds of memories, and proficient peripheral units integration.
Page 16 C166 core. C166S V2 CPU also integrates a multiplication and accumulation unit which dramatically increases performance of the DSP-intensive tasks. C166S V2 CPU has eight main units that are listed below. All of these units have been optimized to achieve maximum performance and flexibility.
Page 17: Register Description Format
Central Processing Unit Register Description Format C166S V2 CPU contains a set of Special Function Register (SFR) and Extended Special Function Registers (ESFR). They are described in the respective chapter of this manual. The example below shows how to interpret the format and notation used to describe SFRs and ESFRs.
Page 18: Cpu Special Function Registers
User Manual C166S V2 Central Processing Unit (* *) * * Register contents after reset ’0/1’ : defined value, ’U’ : unchanged (undefined (’X’) after power up) ’?’ : defined by reset configuration Bit number [m:n] : Bit number first bit of the bitfield...
Page 19: Instruction Fetch And Program Flow Control
User Manual C166S V2 Central Processing Unit Instruction Fetch and Program Flow Control The Instruction Fetch Unit (IFU) pre-fetches and pre-processes instructions to provide a continuous instruction flow. The IFU can fetch simultaneously at least two instructions via a 64-bit wide bus from the Program Management Unit (PMU). The pre-fetched instructions are stored in an instruction FIFO.
Page 20: Branch Target Addressing Modes
User Manual C166S V2 Central Processing Unit During the pre-fetch stage, the Branch Detection and Prediction Logic analyzes up to three pre-fetched instructions stored in the first Instruction Buffer (up to six instructions). If a branch is detected, then the IFU starts to fetch the next instructions from the PMU according to the prediction rules.
Page 21 Therefore, the least significant bit of ’caddr’ is not used. seg: Specifies an absolute code segment number. The C166S V2 CPU supports 256 different code segments, so only the eight lower bits (respectively) of the ’seg’ operand value are used to update the CSP register.
Page 22: Branch Detection And Branch Prediction
User Manual C166S V2 Central Processing Unit 2.3.2 Branch Detection and Branch Prediction The Branch Detection Unit pre-processes instructions and classifies detected branches. Depending on the branch class, the Branch Prediction Unit predicts the program flow using the rules in the following table:.
Page 23 User Manual C166S V2 Central Processing Unit Note: For JMPA instruction, a pre-fetch hint bit is used (the instruction bit 9 = l). This bit is required by the fetch unit to deal efficiently with short backward loops. It must be set if 0 <...
Page 24: Sequential And Mispredicted Instruction Flow
User Manual C166S V2 Central Processing Unit 2.3.3 Sequential and Mispredicted Instruction Flow Because passing through one pipeline stage takes at least one clock cycle, any isolated instruction takes at least five clock cycles to be completed. Pipelining, however, allows parallel (i.e.
Page 25 User Manual C166S V2 Central Processing Unit instructions can be prefetched. The PMU address stays stable (T ) until a whole 64-bit double word can be buffered (T ) in the 96-bit Prefetch buffer again. PMU Address a+16 a+24 a+32...
Page 26: Incorrectly Predicted Instruction Flow
User Manual C166S V2 Central Processing Unit 2.3.3.2 Incorrectly Predicted Instruction Flow If the CPU detects that the IFU made an incorrect prediction of the instruction flow, then the pipeline stages and the Instruction FIFO containing the wrong prefetched instructions are canceled.
Page 27: Atomic And Extend Instructions
User Manual C166S V2 Central Processing Unit PMU Address I... a+16 a+24 PMU Data 64bit I PREFETCH 96-bit Buffer FETCH next+2 Instruction Buffer Fetch from FIFO DECODE next+1 ADDRESS next MEMORY branch EXECUTE branch WRITE BACK branch Figure 2-6 Incorrectly Predicted Instruction Flow 2.3.4...
Page 28: Code Addressing Via Code Segment And Instruction Pointer
CSP register. The IP register is not mapped into the C166S V2 CPU’s address space, and thus it is not directly accessible by the programmer. The IP can be modified indirectly via the stack by return instructions.
Page 29 User Manual C166S V2 Central Processing Unit Field Bits Type Description [15:1] Specifies the intra segment offset from which the current instruction is to be fetched. IP refers to the current segment <SEGNR>. IP is always word-aligned The Code Segment Pointer CSP This non-bit addressable register selects the code segment being used at run-time to access instructions.
Page 30: Ifu Control Registers
IFU Control Registers 2.3.6.1 he CPU Configuration Register CPUCON1 This register is used to configure the C166S V2 CPU. Most bits of this register enable dedicated features of the Instruction Fetch Unit (IFU). CPICON1 may not exist in future product derivatives.
Page 31: The Cpu Configuration Register Cpucon2
2.3.6.2 The CPU Configuration Register CPUCON2 This register is used to configure the C166S V2 CPU. It is an extension of the CPUCON1 register. This register is implemented for test purposes only in the first C166S V2 demonstration devices. This register will not be implemented in production devices.
Page 32 User Manual C166S V2 Central Processing Unit Field Bits Type Description FIFODEPTH [15:12] FIFO Depth configuration 0000 No FIFO (entries) 0001 One FIFO entry ..1000 Eight FIFO entries 1001 reserved 1111 reserved FIFOFED [11:10] FIFO Fed configuration FIFO disabled...
Page 33 User Manual C166S V2 Central Processing Unit Field Bits Type Description FASTBL Enables the fast injection of block transfers Direct injection disabled Direct injection enabled Enables short loop mode Short loop mode disabled Short loop mode enabled enables dedicated stall debug instructions:...
Page 34: Use Of General Purpose Registers
Central Processing Unit Use of General Purpose Registers The C166S V2 CPU uses several banks of sixteen dedicated registers R0, R1, R2... R15, called General Purpose Registers (GPR), which can be accessed in one CPU cycle. The GPRs are the working registers of the arithmetic and logic units and many also serve as address pointers for indirect addressing modes.
Page 35 User Manual C166S V2 Central Processing Unit The register file is split into three independent physical register banks. Because of behavior differences, the banks can be distinguished as global and local register banks. There are two local and one global register bank.
Page 36: Memory Mapped Gpr Banks And The Global Register Bank
2.4.1 Memory Mapped GPR Banks and the Global Register Bank The C166S V2 CPU uses the global register bank to cache an active memory-mapped GPR bank selected by the Context Pointer (CP). The CP register value determines the address of the first General Purpose Register (GPR) within the DPRAM of up to 16 wordwide and/or bytewide GPRs and selects the memory area which is automatically cached in the global register bank.
Page 37 User Manual C166S V2 Central Processing Unit For some instructions, only the first four GPRs can be used as indirect address pointers. These GPRs are specified via short 2-bit GPR addresses. The respective physical address calculation is identical with the one for the short 4-bit GPR addresses.
Page 38 User Manual C166S V2 Central Processing Unit Table 2-3 Addressing Modes to Access Word-GPRs Name Physical 8-Bit 4-Bit Description Reset Address Address Address Value (CP)+0 General Purpose Word Register R0 UUUU (CP)+2 General Purpose Word Register R1 UUUU (CP)+4 General Purpose Word Register R2...
Page 39 User Manual C166S V2 Central Processing Unit The respective halves of the byte-accessible registers have special names (see Table 2-4). . Table 2-4 Addressing modes to access Byte-GPRs Name Physical 8-Bit 4-Bit Description Reset Address Address Address Value (CP)+0 General Purpose Byte Register RL0...
Page 40: Local Register Bank
2.4.2 Local Register Bank C166S V2 CPU has two local register banks with sixteen independent GPRs each. Both local register banks are not memory mapped. After a switch to a local register bank, the GPRs are directly accessible. There are two different ways to access an activated local register bank.
Page 41 User Manual C166S V2 Central Processing Unit Processor Status Word SFRb Reset Value: 0000 ILVL BANK USR1 USR0 Field Bits Type Description BANK Reserved for register file bank selection Global register bank Reserved Local register bank 1 Local register bank 2 In case of an interrupt service, the bank switch is automatically executed by updating the PSW.
Page 42: Context Switching Of The Global Register Bank
CP register can use the new value of the changed CP. The C166S V2 CPU switches the complete memory-mapped GPR bank with a single instruction. After switching, the service routine executes within its own separate context.
Page 43 User Manual C166S V2 Central Processing Unit memory register bank is preserved when the service routine terminates, i.e. its contents is available on the next call. Before returning from the service routine (RETI), the previous CP is simply popped from the system stack which returns the registers to the original bank.
Page 44 User Manual C166S V2 Central Processing Unit If the interrupt occurred before the load phase, the entire validation process is restarted from the very beginning. If the store phase has been completed before the interrupt, only the load phase is executed.
Page 45: Data Addressing
The DSP Address Generation Unit contains an additional set of address pointers and offset registers which are used in conjunction with the CoXXX instructions only. The C166S V2 CPU provides a lot of powerful addressing modes for word, byte, and bit data accesses (short, long, indirect). The different addressing modes use different formats and have different scopes.
Page 46: Short Addressing Modes
User Manual C166S V2 Central Processing Unit 2.5.1 Short Addressing Modes All of these addressing modes use an implicit base offset address to specify a 24-bit physical address. Short addressing modes allow access to the GPR, SFR or bit addressable memory space: Physical Address = Base Address + ∆...
Page 47 User Manual C166S V2 Central Processing Unit be addressed via ’reg’. Note that the high byte of an SFR cannot be accessed via the ’reg’ addressing mode. Short ’reg’ addresses in the range from F0 always specify GPRs. In that case, only the lower four bits of ’reg’ are sig- nificant for physical address generation and, therefore, it is identical to the address generation described for the ’Rb’...
Page 48: Long And Indirect Addressing Modes
(DPP) (1 of 4) register used to generate the full 24-bit address (see Figure 2-14). The C166S V2 CPU also supports an override mechanism for the DPP addressing scheme (EXTP(R) and EXTS(R) instructions). See following sections for details. 15 14 13...
Page 49: Addressing Via Data Page Pointer Dpp
User Manual C166S V2 Central Processing Unit 2.5.2.1 Addressing via Data Page Pointer DPP The four non-bit addressable Data Page Pointer registers select up to four different data pages. The lower 10 bits of each DPP register select one of the 1024 possible 16- Kilobyte data pages while the upper 6 bits are reserved for the future use.
Page 50 User Manual C166S V2 Central Processing Unit DPP0 Data Page Pointer 0 Reset Value: 0000 DPP1 Data Page Pointer 1 Reset Value: 0001 DPP2 Data Page Pointer 2 Reset Value: 0002 DPP3 Data Page Pointer 3 Reset Value: 0003 Field...
Page 51: Dpp Override Mechanism In The C166S V2 Cpu
DPPx. 2.5.2.2 DPP Override Mechanism in the C166S V2 CPU The C166S V2 CPU provides an override mechanism for the temporary bypass of the DPP addressing scheme. The EXTP(R) and EXTS(R) instructions override this addressing mechanism. Instruction...
Page 52: Long Addressing Mode
User Manual C166S V2 Central Processing Unit 2.5.2.3 Long Addressing Mode The long addressing mode uses a 16-bit constant value encoded in the instruction format which specifies the data page offset and the DPP. The long addressing mode is referred to by the mnemonic ‘mem’. .
Page 53: Indirect Addressing Modes
User Manual C166S V2 Central Processing Unit 2.5.2.4 Indirect Addressing Modes These addressing modes can be considered as a combination of short and long addressing modes. This means that long 16-bit address is provided indirectly by the contents of a word GPR which is specified directly by a short 4-bit address (’Rw’=0 to 15).
Page 54 User Manual C166S V2 Central Processing Unit Some instructions only use the lowest four word GPRs (R3...R0) as indirect address pointers, which are specified via short 2-bit addresses in that case. Physical addresses are generated from indirect address pointers using the following...
Page 55 User Manual C166S V2 Central Processing Unit The following indirect addressing modes are provided: . Table 2-7 Indirect Addressing Modes Mnemonic Particularities [Rw] Most instructions accept any GPR (R15...R0) as indirect address pointer. Some instructions accept only the lower four GPRs (R3...R0).
Page 56: Dsp Addressing
User Manual C166S V2 Central Processing Unit 2.5.3 DSP Addressing In addition to the Standard Address Generation Unit, the DSP Address Generation Unit provides an additional set of pointer and offset registers. An independent arithmetic unit allows the update of these dedicated pointer registers in parallel with the GPR-Pointer modification of the Standard Address Generation Unit.
Page 57 For CoMOV MAC operation, the IDX pointers are concatenated with the Data Page Pointers, just like normal GPR-Pointers as described in Section 2.5.2.1. The IDX pointer can address the entire C166S V2 memory area without any restrictions. User Manual 2-57 V 1.7, 2001-01...
Page 58 User Manual C166S V2 Central Processing Unit 16-Bit Data Address (IDXx) 15 14 Memory selects DPP FF’0000 DPP3 - 11 DPP2 - 10 FE’0000 DPP1 - 01 DPP0 - 00 15 14 01’0000 00’0000 Page Page offset Segment Segment offset...
Page 59 User Manual C166S V2 Central Processing Unit The Offset Register QX0 and QX1 These two non-bit addressable registers are used only for CoXXX operations which access operands using indirect addressing mode. The QX offset registers are used in conjunction with the IDX pointers.
Page 60 User Manual C166S V2 Central Processing Unit Intermediate Address = (IDXx Address) ± D ; [optional step!] Calculate long 16-bit address: Long Address = (IDXx Pointer) Calculate the physical 24-bit address using the resulting long address and the corresponding DPP register contents (see long ’mem’ addressing modes and DPPi override mechanism for arithmetic CoXXX instructions).
Page 61 User Manual C166S V2 Central Processing Unit Table 2-8 DSP Addressing Modes (cont’d) Mnemonic Particularities with parallel In case of a CoXXXM instruction, the address stored in the specified data move indirect address pointer is automatically pre-incremented by 2 for the parallel move operation.
Page 62 User Manual C166S V2 Central Processing Unit CoXXXMxx [IDX0+],[R2+] Address operations calculate pointer addresses IDXx = IDX0 R2 Address = CP + 2*2 (global register bank) 2) intermediate address of write pointer for the parallel mov operation Intermediate Address = (IDX0) - 2...
Page 63: The Coreg Addressing Mode
User Manual C166S V2 Central Processing Unit 2.5.4 The CoREG Addressing Mode The CoSTORE instruction utilizes the special CoREG addressing mode for immediate storage of the MAC-Unit register after a MAC operation. The address of the MAC-Unit register is coded in the CoSTORE instruction format as described in the following table:...
Page 64: The System Stack
2.5.5 The System Stack The C166S V2 CPU supports a system stack of 64 kBytes. The stack can be located internally in one of the on-chip memories or externally. The 16-bit Stack Pointer (SP) register addresses the stack within a 64 kByte segment. The Stack Pointer Segment Register (SPSG) selects the segment in which the stack is located.
Page 65 User Manual C166S V2 Central Processing Unit The Stack Pointer Segment Register SPSEG This non-bit addressable register selects the segment being used at run-time to access system stack. The lower eight bits of register SPSEG select one of up 256 segments of 64-kilobytes each, while the higher 8 bits are reserved for future use.
Page 66 User Manual C166S V2 Central Processing Unit Note: Due to the internal instruction pipeline, a write operation to the SPSG register stalls the instruction flow until the SPSG register is really updated. The instruction immediately following the instruction updating the SPSG register can use the new value.
Page 67 User Manual C166S V2 Central Processing Unit trigger the corresponding trap. Note that event (SP) = (STKOV) resulting from an explicit SP modification does not trigger the trap. The Stack Overflow Trap is triggered when (SP) = (STKOV) and if SP is to be implicitly decremented.
Page 68: Data Processing
All standard arithmetic, shift and logical operations are performed in the 16-bit ALU. In addition to the standard arithmetic and logic unit, the ALU of the C166S V2 CPU includes bit manipulation, multiply and divide unit. Most internal execution blocks have been optimized to perform operations on either 8-bit or 16-bit numbers.
Page 69 C166S V2 Central Processing Unit The C166S V2 CPU data formats are able to support all ANSI C data types. Additional to the ANSI C data types, some C-Compilers support new types that allow efficient use of the bit manipulation instructions in embedded control applications.. .
Page 70: Constants
2.6.4 Bit Manipulation Unit C166S V2 CPU offers a large number of instructions for bit processing. The special bit manipulation unit was implemented for this purpose. The bit manipulation instructions enable efficient control and testing of peripherals. Unlike other microcontrollers,...
Page 71: Multiply And Divide Unit
2.6.5 Multiply and Divide Unit The C166S V2 CPU multiply and divide unit has two separated parts. One is the fast 16x16-bit multiplier that executes a multiplication in one CPU cycle. The other one is a division sub-unit which performs the division algorithm in 21 CPU cycles maximum.
Page 72 User Manual C166S V2 Central Processing Unit seventeen CPU cycles, while further instructions are executed in parallel. If another instruction tries to use the unit while a division is still running, the execution of this new instruction is stalled until the division is finished.
Page 73 User Manual C166S V2 Central Processing Unit multiplication, this register represents the low order sixteen bits of the 32-bit result. For long divisions, the MDL register must be loaded with the low order sixteen bits of the 32-bit dividend before the division has started. After any division, the MDL register represents the 16-bit quotient.
Page 74: The Processor Status Word Psw
The MDRIU flag is the only portion of the MDC register used for multiplication and division within the C166S V2 CPU. This bit indicates the usage of the MDL and MDH register. It must be stored prior to a new multiplication or division operation. The remaining portions of the MDC register are never used by the dedicated multiplication and division hardware.
Page 75 User Manual C166S V2 Central Processing Unit Field Bits Type Description MULIP Multiplication/Division in progress Always set to 0 End of Table Flag Source operand is neither 8000 nor 80 Source operand is 8000 or 80 Zero Flag ALU result is not zero...
Page 76 User Manual C166S V2 Central Processing Unit • C-Flag: After an addition, the C-flag indicates that a “Carry” from the most significant bit of the specified word or byte data type has been generated. After a subtraction or a comparison, the C-flag indicates a “Borrow” which represents the logical negation of a “Carry”...
Page 77 Note: The MULIP flag is a part of the C166 task environment. For compatibility reasons, the bit is still implemented even if not used. A multiply and divide ALU operation of the C166S V2 CPU is no longer interruptible. • BANK: The BANK bitfield of the PSW registers indicates which one of the three physical register banks is activated.
Page 78: Parallel Data Processing
User Manual C166S V2 Central Processing Unit priority, and thus the current CPU operation cannot be interrupted except by hardware traps or external non-maskable interrupts. For details please, refer to Section 5 “Interrupt and Trap Functions”. After reset, all interrupts are globally disabled and the lowest priority (ILVL=0) is assigned to the initial CPU activity.
Page 79: Representation Of Numbers And Rounding
2.7.1 Representation of Numbers and Rounding The C166S V2 CPU supports the 2s complement representation of binary numbers. In this format, the sign bit is the MSB of the binary word. This is set to zero for positive numbers and set to one for negative numbers. Unsigned numbers are supported only by multiply/multiply-accumulate instructions which specify whether each operand is signed or unsigned.
Page 80: The 16-Bit By 16-Bit Signed/Unsigned Multiplier And Scaler
User Manual C166S V2 Central Processing Unit The C166S V2 CPU implements 2s complement rounding’. With this rounding type, one is added to the bit to the right of the rounding point (bit 15 of MAL), before truncation (MAL is cleared).
Page 81: The 40-Bit Adder/Subtracter
User Manual C166S V2 Central Processing Unit • MP-Control Bit: If the MP mode bit is set and both multiplier operands are signed types, the multiplier output is automatically shifted left by one bit. In the case of a multiply and accumulate operation, the output of the multiplier is shifted before being added to the accumulator.
Page 82: The Accumulator Shifter
User Manual C166S V2 Central Processing Unit performed on the MAC-Unit accumulator. If the contents of the Accumulator can be represented in the destination operand size without overflow, then the data limiter is disabled and the operand is not modified. If the contents of the accumulator cannot be represented without overflow in the destination operand size, the limiter will substitute a “limited”...
Page 83 User Manual C166S V2 Central Processing Unit number (MAH has 1 in the most significant bit), the MAE will be loaded with ones, representing the extended 40-bit negative number in 2s compliment notation. One may see that the extended 40-bit value is equal to 32-bit value without extension. In other words, after this extension, MAE does not contain significant bits.
Page 84: The Repeat Counter Mrw
User Manual C166S V2 Central Processing Unit Accumulator High Word Reset Value: 0000 Field Bits Type Description [15:0] High part of Accumulator The middle (bits 31 to 16) word of the 40-bit MAC Accumulator. The MAC Unit Accumulator Low Word MAL The MAL register is a part of the 40-bit MAC unit accumulator register.
Page 85: The Mac Unit Status Word Msw
User Manual C166S V2 Central Processing Unit the MRW equals zero, the USRx bit is set and MRW is not further decremented. The MRW can be accessed via any instruction capable of accessing a SFR. MAC Repeat Word SFRb Reset Value: 0000...
Page 86 User Manual C166S V2 Central Processing Unit MAC Unit Status (MV, MN, MZ, MC, MSV, ME, MSL) The condition flags (MV, MN, MZ, MC, MSV, ME, MSL) within the MSW indicate the MAC resulting from the most recently performed MAC operation. These flags are controlled by the majority of the MAC instructions according to specific rules.
Page 87 User Manual C166S V2 Central Processing Unit Field Bits Type Description [12] MAC Extension Flag MAE does not contain significant bits MAE contains significant bits [13] Sticky Limit Flag Result was not saturated Result was saturated [14] Overflow Flag No Overflow produced Overflow produced •...
Page 88: The Mac Unit Control Word Mcw
User Manual C166S V2 Central Processing Unit numbers. If the MSV-flag indicates an arithmetic overflow, the MAC result of an operation is not valid. The MSV-flag is a ’Sticky Bit’. Once set, other MAC operations cannot affect the status of the MSV-flag. Only a direct write operation can clear the MSV-flag.
Page 89: Dedicated Csfrs
User Manual C166S V2 Central Processing Unit • MS-Control Bit: If the MS mode bit is set, the accumulator will be automatically saturated to 32 bits. The MAC Unit supports signed saturation. • MP-Control Bit: If the MP mode bit is set and both multiplier operands are of signed types, the multiplier output is automatically shifted left by one bit.
Page 90 C166S V2 core module. CPUID CPU Identification Register ESFR Reset Value: 03?? MODULE NUMBER VERSION NUMBER Field Bits Type Description MODULE NUMBER [15:8] Module Number C166S V2 core module number VERSION NUMBER [7:0] Version Number Version Number User Manual 2-90 V 1.7, 2001-01...
Page 91: C166S V2 Memory Organization
C166S V2 Memory Organization C166S V2 Memory Organization The memory space of the C166S V2 CPU is configured in a “Von Neumann” architecture. This means that code and data are accessed within the same linear address space. All of the physically separated memory areas, including internal ROM/...
Page 92 User Manual C166S V2 C166S V2 Memory Organization FF´FFFF Segment Data Page 1023 FF´0000 C0´0000 Segment reserved 00’FFFF BF´0000 RAM / 00’F000 internal-IO Area Data Page 3 41´0000 00’E000 Segment Internal SRAM 00’C000 40´0000 Internal SRAM Data Page 2 21´0000 Segment 00’8000...
Page 93: Data Organization In Memory
(internal, external, ROM, RAM) and organizational (page, segment) memory area. Internal Program Memory The C166S V2 CPU reserves an address area of 4 MBytes for Internal Program Memory. The internal memory can be ROM, SRAM, Flash or DRAM. Devices with...
Page 94: Dpram, Internal Sram, And Sfr Areas
Note: The ‘x’ in the locations above depend on the available Internal Program Memory. DPRAM, Internal SRAM, and SFR Areas The C166S V2 CPU differentiates between various internal memory types and internal peripheral areas. These data memories and the IO/SFR areas are located within data...
Page 95 User Manual C166S V2 C166S V2 Memory Organization data access is made on an even byte address. The highest possible word data storage location in the DPRAM is 0000’FDFE A 24 kByte memory area (00‘8000 ...000’DFFF ) is reserved for the Internal SRAM. Any word and byte data in the Internal SRAM can be accessed via indirect or long 16-bit addressing modes, if the selected DPP register points to data page 3 or data page 2.
Page 96: Special Function Register Areas
The functions of the CPU, the bus interface, the IO ports, and the on-chip peripherals of the C166S V2 device are controlled via a number of so-called Special Function Registers (SFRs). These SFRs are arranged within two areas of 512 Bytes each. The first register block, the SFR area, is located in the 512 Bytes above the DPRAM (00’FE00...
Page 97: Io Area
Some parts of the C166S V2 CPU memory area are marked as IO. These memory areas have the following special properties: – Accesses are not buffered and cached The write back buffers and caches of the C166S V2 CPU are not used to store IO read and write accesses. – Special handling of destructive reads The pipeline of the C166S V2 CPU allows speculative reads.
Page 98: External Memory Space
“Interrupt and Exception Execution” section. External Memory Space The C166S V2 CPU is capable of using an address space of up to 16 MBytes. Only portions of this address space are occupied by internal memory areas. All addresses not used for on-chip memory or for registers may reference external memory locations.
Page 99: Crossing Memory Boundaries
(SPSEG) represents the high order 8 bits of the stack pointer, also referred to as Stack Segment. The system stack implementation in the C166S V2 CPU is from high to low memory. The system stack grows downward as it is filled. The SP register is decremented first each...
Page 100: Data Organization In Global General Purpose Registers
The C166S V2 CPU differentiates between global memory mapped General Purpose Register (GPR) banks and local not mapped GPR banks. In addition to the memory mapped register banks, the C166S V2 CPU has two local not memory mapped GPR register banks for very fast context switching (see Section 2.4).
Page 101 User Manual C166S V2 C166S V2 Memory Organization Mapping of the global General Purpose Registers to DPRAM Addresses is shown here: DPRAM Address Byte Registers Word Register <CP> + 1E <CP> + 1C <CP> + 1A <CP> + 18 <CP> + 16 <CP>...
Page 102 User Manual C166S V2 C166S V2 Memory Organization User Manual 3-102 V 1.7, 2001-01...
Page 103: Instruction Pipeline
Instruction Pipeline Instruction Pipeline The pipeline of the C166S V2 CPU has seven stages. Each stage processes its individual task. The first two stages form the instruction fetch pipeline and the remaining five stages constitute the instruction processing pipeline. The instruction fetch pipeline is used to pre-fetch instructions and to store them into an instruction FIFO.
Page 104: Instruction Dependencies In Different Pipeline Stages
4.1.1 The General Purpose Registers The GPRs are the working registers of the C166S V2 CPU and there are a lot of possible dependencies between instructions using GPRs. A high speed five port register file prevents bandwidth conflicts. The dedicated hardware is implemented to detect and resolve the data dependencies.
Page 105 User Manual C166S V2 Instruction Pipeline R6,R0 R6,R1 ..DECODE ADD R0,R1 ADD R3,R0 ADD R6,R0 ADD R6,R1 ADDRESS ADD R0,R1 ADD R3,R0 ADD R6,R0 ADD R6,R1 MEMORY ADD R0,R1 ADD R3,R0 ADD R6,R0 ADD R6,R1 EXECUTE ADD R0,R1 ADD R3,R0...
Page 106: Indirect Addressing Modes
User Manual C166S V2 Instruction Pipeline ..R0,R1 R3,[R0] R6,R0 R6,R1 ..DECODE ADD R0,R1 MOV R3,[R0] ADDRESS ADD R0,R1 MOV R3,[R0] MOV R3,[R0] MOV R3,[R0] MEMORY ADD R0,R1 MOV R3,[R0] EXECUTE ADD R0,R1 WRITE BACK ADD R0,R1 To avoid stalls, one multicycle or two single cycle instructions may be inserted. These instructions must not update the GPR used for indirect addressing.
Page 107: Memory Bandwidth Conflicts
Memory bandwidth conflicts can occur if instructions in the pipeline access the same memory area at the same time. Special access mechanisms are implemented in the C166S V2 CPU to minimize conflicts. The internal DPRAM of the C166S V2 CPU has User Manual 4-107 V 1.7, 2001-01...
Page 108 User Manual C166S V2 Instruction Pipeline two independent read/write ports; this allows parallel read and write operation without delays. Write accesses to the internal SRAM can be buffered in a Write BACK Buffer until read accesses are finished. • Bandwidth conflicts in the DPRAM Area All instructions except the CoXXX instructions can read only one memory operand per cycle.
Page 109 User Manual C166S V2 Instruction Pipeline • Bandwidth conflicts in the DPRAM Area The CoXXX instructions are the only instructions able to read two memory operands per cycle. A conflict between the two read and one pending write access can occur if all three operands are located in the DPRAM areas.
Page 110: Cpu-Sfrs And The Pipeline
Executed stage of the pipeline. Meanwhile, without conflict detection, the instructions in the Decode, Address, and Memory stages would still work without updated register values. The C166S V2 CPU detects conflict cases and stalls the pipeline to guarantee a correct execution. For performance reasons, the CPU differentiates between different classes of CPU-SFRs.
Page 111 User Manual C166S V2 Instruction Pipeline updated in the Execute Stage and is not used for control purposes in the previous stages. CPUID, ONES, and ZEROS are not changeable at all..MCW,#16 R6,R0 R6,R1 R3,[R0] ..DECODE MOV MCW,#16...
Page 112 User Manual C166S V2 Instruction Pipeline • The CSFR result registers MDH, MDL, MSW, MAH, MAL, MRW of the ALU and MAC- Unit are updated late in the Execute stage of the pipeline. If an instruction (except CoSTORE) accesses explicitly these registers in the memory stage, the value cannot be forwarded.
Page 113 User Manual C166S V2 Instruction Pipeline • The third class are CSFRs which affect the whole CPU or the pipeline before the Memory stage. The CPU-SFRs CPUCON1, CP, SP, STKUN, STKOV, VECSEG, TFR, and PSW affect the overall CPU functioning while the C-SFRs IDX0, IDX1, QX1, QX0, DPP0, DPP1, DPP2 and DPP3 only affect the Decode, Address, and Memory stage when they are modified explicitly.
Page 114 User Manual C166S V2 Instruction Pipeline ..IDX1,#12 R6,mem R6,R1 R3,[R0] ..DECODE MOV IDX1,#12 MOV R6,mem MOV R6,mem MOV R6,mem MOV R6,mem ADD R6,R1 ADDRESS MOV IDX1,#12 MOV R6,mem MEMORY MOV IDX1,#12 EXECUTE MOV IDX1,#12 WRITE BACK MOV IDX1,#12 ..
Page 115 User Manual C166S V2 Instruction Pipeline – For all the other instructions that modify this kind of CSFR, a simple stall and cancel mechanism guarantees the correct instruction flow. A possible explicit write-operation to this kind of CSFRs is detected on the Memory stage of the pipeline.
Page 116 User Manual C166S V2 Instruction Pipeline User Manual 4-116 V 1.7, 2001-01...
Page 117: Interrupt And Exception Handling
Interrupt Processing via the Peripheral Event Controller (PEC) A faster alternative to normal interrupt processing uses the C166S V2 CPU's integrated Peripheral Event Controller (PEC) to service an interrupt requesting device. Triggered by an interrupt request, the PEC performs a single word or byte data transfer between any two memory locations.
Page 118: Interrupt System And Control
5.1.1 General Interrupt System Structure The C166S V2 CPU can provide up to 128 separate interrupt nodes that may be assigned to sixteen interrupt priority levels with four sub-priorities inside each level (group priority) for up to 64 interrupt nodes or with eight sub-priorities inside each level (group priority) in the case of more than 64 interrupt nodes.
Page 119 User Manual C166S V2 Interrupt and Exception Handling Interrupt and Peripheral Event Controller Interrupt PEC Pointer Request Lines SRCP0 DSTP0 PECSEG0 SRCP1 DSTP1 PECSEG1 irq0 SRCP7 DSTP7 PECSEG7 irq1 C166S V2 irq2 irq3 Arbitration PEC Request Arbitr. Request Request Injection...
Page 120: Interrupt Arbitration
5.1.2 Interrupt Arbitration The C166S V2 interrupt arbitration system can handle interrupt requests from up to 128 sources. Interrupt requests may be triggered either by the C166S V2 peripherals or by external inputs. The “End of PEC” interrupt for supporting enhanced PEC functionality is connected internally to one interrupt request line.
Page 121 The second arbitration stage compares the priority of the first stage winner with the priority of OCDS service requests. C166S V2 OCDS service requests bypass the first stage of arbitration and go directly to the CPU Action Control Unit. The CPU Action Control Unit disregards the group priority level of interrupt/PEC requests and deals only with interrupt priority levels (ILVL).
Page 122: Interrupt Control
User Manual C166S V2 Interrupt and Exception Handling win the second stage arbitration. However, if there is a OCDS request with MSB=0 conflicting with the same priority interrupt/PEC request, the latter is sent to the CPU. On the third arbitration stage, the priority level of the second stage winner is compared with the priority of the current CPU task.
Page 123 User Manual C166S V2 Interrupt and Exception Handling xxIC Interrupt Control Register Reset Value: 0000 GPX xxIR xxIE ILVL GLVL Field Bits Type Description Group Priority Extension Defines the value of high-order group level bit xxIR Interrupt Request Flag No request pending...
Page 124: Interrupt Vector Table
The reserved vector locations are assembled into a vector table located in the address space of the C166S V2. The vector table contains the appropriate jump instructions that transfer control to the interrupt or trap service routines. These routines may be located anywhere within the address space.
Page 125: Interrupt Jump Table Cache
Interrupt Controller (ITC). For a very fast interrupt response time, the C166S V2 offers a new feature of the interrupt system— Interrupt Jump Table Cache (also called “fast interrupt”). The ITC can transfer a 24-bit vector to the CPU that is used directly as a start address for the service routine.
Page 126 User Manual C166S V2 Interrupt and Exception Handling respective control registers. The two upper bits of the interrupt priority level are set to ‘11 ’, which limits the allowed interrupt priority level to be greater than or equal to 12.
Page 127: Status And Switch Context Control
The Processor Status Word (PSW) is functionally divided into two parts: the lower byte of the PSW represents the arithmetic status of the CPU, the upper byte of the PSW controls the interrupt system of the C166S V2 CPU. Note: For a summary of the PSW register, please refer to Section 2.6.6...
Page 128 User Manual C166S V2 Interrupt and Exception Handling Processor Status Word bSFR Reset Value: 0000 ILVL BANK USR1 USR0 Field Bits Type Description ILVL [15:12] rwh CPU Priority Level Lowest Priority Highest Priority [11] Interrupt/PEC Enable Bit (globally) Interrupt/PEC requests are disabled...
Page 129: Saving The Status During Interrupt Service
Before an operating system or ITC can actually service a task switch request or interrupt, the CPU must save the current task status. The C166S V2 CPU saves the CPU status (PSW) along with the return address in the system stack. The return address defines the point at which the execution of the interrupted task is to be resumed after returning from the service routine.
Page 130: Context Switching
The C166S V2 CPU allows the complete bank of CPU registers (GPRs) to be switched, so the service routine executes within its own separate context. There are two ways to switch a context in the C166S V2 core (for details, see Section 2.4.3):...
Page 131: Fast Bank Switching
Interrupt and Exception Handling 2. Switching Context of the Global Register Bank by Changing Context Pointer The C166S V2 CPU allows the complete global register bank of CPU registers (GPRs) to be changed with a single instruction; so, the service routine executes within its own separate context.
Page 132: Traps
User Manual C166S V2 Interrupt and Exception Handling Table 5-1 identifies the arbitration priority level assignment to the respective bit fields within the four register bank selection registers: Table 5-1 Register Bank Assignment Interrupt Group Assigned Interrupt Group Assigned Priority...
Page 133: Hardware Traps
– Selects the global register bank for the trap service routine – Branches to the trap vector location specified by the trap number of the trap condition The eight hardware functions of the C166S V2 CPU are divided in two classes: Class A and Class B.
Page 134 User Manual C166S V2 Interrupt and Exception Handling Class B traps are: – Undefined Opcode – Parity Fault – Protection Fault – Illegal Word Operand Access The Class B traps share the same interrupt node and interrupt vector. The bit addressable Trap Flag Register (TFR) allows a trap service routine to identify the trap that caused the exception.
Page 135 User Manual C166S V2 Interrupt and Exception Handling Field Bits Type Description PRTFLT Protection Fault No protection fault event detected Protection fault event detected ILLOPA Illegal word operand access No illegal word operand access event detected Illegal word operand access event detected This Bit supports bit-protection Parity fault on instruction fetch interface, usable for memories with parity check.
Page 136 User Manual C166S V2 Interrupt and Exception Handling not used to indicate hardware failures. After a Class A event, a dedicated service routine is called to react to the events. Each Class A trap has its own vector location in the vector table.
Page 137 User Manual C166S V2 Interrupt and Exception Handling The Parity Fault is an asynchronous external event while all other Class B traps are generated in the pipeline during the execution of instructions. It is not possible for two different instructions in the pipeline to generate Class A and Class B traps in the same CPU cycle.
Page 138: Peripheral Event Controller
• Parity Fault Trap: When a parity error is detected in the system, the PARFLT flag is set in register TFR and the CPU enters the parity fault trap routine. For the C166S V2 CPU, the parity fault is an asynchronous system event. There is no link between the fault and the instruction flow itself.
Page 139: Pec Control Registers
User Manual C166S V2 Interrupt and Exception Handling 5.4.1 PEC Control Registers Each PEC channel is controlled by the respective PEC channel Control register (PECCx) and a set of source and destination pointers (SRCPx, DSTPx and PECSEGx), where ‘x’ stands for the PEC channel number. The PECCx registers control the arbitration priority level assignment to the PEC channels and the action to be performed.
Page 140 User Manual C166S V2 Interrupt and Exception Handling Field Bits Type Description Byte/Word Transfer Selection Transfer a word Transfer a byte COUNT [7:0] PEC Transfer Count Counts PEC transfers and influences the channel´s action (see section below) The Byte/Word Transfer bit (BWT) of the PECCx register determines if a byte or a word is to be moved during a PEC service cycle and defines an increment step size for the pointer(s) to be modified.
Page 141 User Manual C166S V2 Interrupt and Exception Handling EOPIC Interrupt Control Register bESFR Reset Value: 0000 GPX EOP ILVL GLVL The EOPIC register is assigned to one of the interrupt nodes. The assignment is product specific. Field Bits Type Description...
Page 142 User Manual C166S V2 Interrupt and Exception Handling Field Bits Type Description CxIR 15, 13, Interrupt Sub Node Request Flag of PEC 1) 2) 11, 9, Channel x 7, 5, 3, No special end of PEC interrupt request is pending for PEC channel x...
Page 143 User Manual C166S V2 Interrupt and Exception Handling PECISNC C7IR C7IE C6IR C6IE C5IR C5IE C4IR C4IE C3IR C3IE C2IR C2IE C1IR C1IE C0IR C0IE Interrupt Request Pulse Generator EOPIC ILVL GLVL Figure 5-4 End of PEC Interrupt Sub Node...
Page 144 User Manual C166S V2 Interrupt and Exception Handling Table 5-3 PEC Channel Actions Previous Modified Action of PEC Channel COUNT Field COUNT Field and Comments Value Value Move a Byte/Word Continuous transfer mode; COUNT is not modified ...02 ...01 Move a Byte/Word and decrement COUNT...
Page 145: The Pec Source And Destination Pointer
User Manual C166S V2 Interrupt and Exception Handling transfers are then controlled by the partner channel the finished channel can be reconfigured. The termination of the transfers of a linked channel is indicated by the triggering of an interrupt. If the channel link bit CL of the active channel or the EOPINT flag is set a End of PEC interrupt is called.
Page 146 User Manual C166S V2 Interrupt and Exception Handling PECSEGx SRCSEGx DSTSEGx SRCPx DSTPx SRCPx DSTPx Source Pointer Destination Pointer 16 15 16 15 Segment Address Segment Offset Segment Address Segment Offset Data Transfer x = 7...0, depending on PEC channel number...
Page 147: Pec Handler Interrupt Actions Summary
User Manual C166S V2 Interrupt and Exception Handling that points to an even byte boundary. Otherwise, the Illegal Word Access trap will be invoked when this channel is used. SRCPx PEC Source Pointer (x=7-0) XSFR Reset Value: 0000 SRCPx Field...
Page 148 User Manual C166S V2 Interrupt and Exception Handling Field Bits Type Description SRCSEGx [15:8] Source Pointer Segment Address of Channel x Source Address bits 23-16 DSTSEGx [7:0] Destination Pointer Segment Address of Channel x Destination Address bits 23-16 • PEC channel is enabled and the bit field COUNT has a value higher than ‘01...
Page 149: Pec Channel Assignment And Arbitration
5.4.4 PEC Channel Assignment and Arbitration The C166S V2 PEC channels can be assigned to a certain arbitration priority level. All requests with interrupt priority levels 8 to 15 and group levels 0 to 3 can be associated with the PEC functionality (eight PEC channels in total). The group extension is not supported for PEC requests, because the 8 PEC channels are assigned to two interrupt levels for compatibility to the C16x family.
Page 150 User Manual C166S V2 Interrupt and Exception Handling Table 5-4 PEC Channel Assignment Arbitration Priority Arbitration Priority Level Channel x Level Channel x Interrupt Group PLEV Ch Interrupt Group PLEV Ch Priority Priority Priority Priority Level Level Level Level xxIC.ILVL xxIC.XGLVL...
Page 151: Cpu Action Control Unit
User Manual C166S V2 Interrupt and Exception Handling CPU Action Control Unit The CPU Action Control Unit multiplexes interrupt/PEC requests with OCDS requests and forwards them to the CPU demanding the corresponding action. It also routes request acknowledges and denies from the core to the corresponding requester. The OCDS requests have programmable priority levels.
Page 152 User Manual C166S V2 Interrupt and Exception Handling User Manual 5-152 V 1.7, 2001-01...
Page 153: External Bus Controller
Although the C166S V2 products provide a powerful set of on-chip peripherals and on- chip program and data memories, these internal units only cover a small fraction of the C166S V2´s address space of up to 16 MByte. The external bus interface allows access to external peripherals and additional volatile and non-volatile memories.
Page 154: Timing Principles
User Manual C166S V2 External Bus Controller Timing Principles The EBC supports four different access types. Reads and Writes in multiplexed and demultiplexed mode. Multiplexed mode means that the data bus is used in a ‘time- multiplex’ for address (the 16 LSBs) and for data. In demultiplexed mode the data bus is used for data only and an additional 16 bit address bus is available.
Page 155 User Manual C166S V2 External Bus Controller Figure 6-1 Demultiplexed Bus Read valid ADDR, CS read DATA valid 1-32 clock cycles needed bits Figure 6-2 Demultiplexed Bus Write ADDR, CS valid valid write DATA 1-32 clock cycles needed bits • a phase: addresses valid, ALE high, no command. CS switch tristate wait states •...
Page 156 User Manual C166S V2 External Bus Controller Figure 6-3 Multiplexed Bus Read ADDR, CS valid read DATA addr valid data in valid clocks 1-32 needed bits Figure 6-4 Multiplexed Bus Write ADDR, CS valid address valid write DATA data out valid...
Page 157: A Phase
User Manual C166S V2 External Bus Controller 6.2.1 A Phase The A phase can take 0-3 clocks. It is used to tristate the databus drivers activated in the previous cycle (tristate wait states after CS switch). Phase A cycles are not inserted in every access cycle but only when changing the CS.
Page 158: F Phase
All EBC registers are write protected by the EINIT protection mechanism. This means that after execution of the EINIT instruction by the C166S V2 CPU these registers are not writeable anymore. For a list of all EBC control registers refer to Chapter 9.4.
Page 159 User Manual C166S V2 External Bus Controller Field Bits Description RDYPOL READY pin Polarity READY is active low READY is active high RDYDIS READY pin Disable READY enabled READY disabled ALEDIS ALE pin Disable ALE enabled ALE disabled BYTDIS BHE pin Disable...
Page 160 User Manual C166S V2 External Bus Controller Field Bits Description CSPEN [7:4] CS Pins Enable 0000 no chipselect pins enabled 0001 enables pin CS0 1000 enables pins CS7, ..., CS0 else reserved SAPEN [3:0] Segment Addresses Pins Enable 0000 no segment address pin enabled...
Page 161: The Timing Configuration Registers Tconcsx
User Manual C166S V2 External Bus Controller 6.3.3 The Timing Configuration registers TCONCSx The timing control registers are used to program the described cycle timing for the different access phases. The timing control registers may be reprogrammed during code fetches from the affected address window. The new settings are first valid for the next access.
Page 162 User Manual C166S V2 External Bus Controller Field Bits Description Reserved The software always reads a ’0’. Although this bit is read only, the software should always write a ’0’ in case of a write access. WRPHF [14:13] rw Write Phase F...
Page 163: The Function Configuration Registers Fconcsx
User Manual C166S V2 External Bus Controller 6.3.4 The Function Configuration Registers FCONCSx The Function Control registers are used to control the bus and ready functionality for a selected address window. It can be distinguished between 8 and 16 bit bus and multiplexed and demulitplexed accesses.
Page 164: The Address Window Selection Registers Addrselx
Definition of Address Areas The seven register sets FCONCS1/TCONCS1/ADDRSEL1 to FCONCS7/TCONCS7/ ADDRSEL7 define seven separate address areas within the address space of the C166S V2. Within each of these address areas external accesses can be driven in one User Manual 6-164...
Page 165 The size of these two address areas is fixed to 32 kByte. The address area from 00’8000 to 00’FFFF (32 kbyte) is reserved for C166S V2 CPU internal I/O, the area from BF’0000 to BF’FFFF (64 kbyte) for startup and monitor memory and the area from C0’0000...
Page 166: Address Window Arbitration
User Manual C166S V2 External Bus Controller 6.3.5.2 Address Window Arbitration For each external access the EBC compares the current address with all address select registers (programmable ADDRSELx and hardwired address select registers for startup and monitor memory) of enabled windows. This comparison is done in four levels.
Page 167: Ready Controlled Bus Cycles
For situations, where the response (access) time of a peripheral is not constant, or where the programmable wait states are not enough, the C166S V2 EBC provides external bus cycles that are terminated via a READY input signal. In this case during phase E the C166S V2 EBC first counts a programmable number of clock cycles (1...32) and starts...
Page 168: The Synchronous/Asynchronous Ready
READY signal when a cycle was started. After a predefined number of clock cycles the C166S V2 will start checking its READY line to determine the end of the bus cycle. When using the READY function with so-called ‘normally-ready’ peripherals, it may lead to erroneous bus cycles, if the READY line is sampled too early.
Page 169: Ebc Idle State
This bus arbitration allows an external master to request the C166S V2’s bus. The C166S V2 will release the external bus and will float the data and address bus lines and force the control signals via pull ups/downs to their inactive state.
Page 170: Arbitration Master Scheme
6.4.1.2 Arbitration Master Scheme If the C166S V2 EBC is configured as arbitration master, it is default owner of the external bus, controls the arbitration protocol and drives the bus also during idle phases with no bus requests. To perform the arbitration handshake a HOLD input allows the request of the external bus from the arbitration master.
Page 171: Arbitration Slave Scheme
Arbitration Slave Scheme If the C166S V2 EBC is configured as arbitration slave it is by default not owner of the external bus and has to request the bus first. As long as it has not finished all its queued requests and the arbitration master is not requesting the bus the arbitration slave stays owner of the bus.
Page 172: Connecting Multimaster Systems
C166S V2 External Bus Controller by setting the PSW bit HLDEN to ‘0’. In this case the looked C166S V2 EBC will not answer to HOLD requests from other external bus master until HLDEN is set to ‘1’ again. Of course a looked bus master not owning the bus can request the external bus. If a master and a slave are requesting the external bus at the same time for several accesses, they toggle the ownership after each access cycle if the bus is not locked.
Page 173: Fastest Possible External Access
User Manual C166S V2 External Bus Controller Fastest possible external access The following four figures show the principal possible fastest access type for the EBC. Figure 6-11 Fastest Read Cycle Demultiplexed Bus valid ADDR, CS valid DATA in Figure 6-12...
Page 174 User Manual C166S V2 External Bus Controller Figure 6-13 Fastest Read Cycle Multiplexed Bus valid ADDR, CS add valid muxed Address out / DATA in d.valid Figure 6-14 Fastest Write Cycle Multiplexed Bus valid ADDR, CS addr valid valid muxed Address out / DATA out...
Page 175: Instruction Set
User Manual C166S V2 Instruction Set Instruction Set Short Instruction Summary The following compressed cross-reference tables quickly identify specific instructions and provide basic information about them Two ordering schemes are included: The first table (two pages) is a compressed cross-reference table that quickly associates specific hexadecimal opcodes with the corresponding mnemonics.
Page 176 User Manual C166S V2 Instruction Set x0 ADD ADDC SUBC x1 ADDB ADDCB SUBB SUBCB CMPB XORB ANDB x2 ADD ADDC SUBC x3 ADDB ADDCB SUBB SUBCB CMPB XORB ANDB x4 ADD ADDC SUBC x5 ADDB ADDCB SUBB SUBCB XORB...
Page 177 User Manual C166S V2 Instruction Set x0 CMPI1 CMPI2 CMPD1 CMPD2 MOVBZ MOVBS MOV x1 NEG NEGB CPLB MOVB MOVB EXTR x2 CMPI1 CMPI2 CMPD1 CMPD2 MOVBZ MOVBS PCALL x3 CoXXX CoXXX CoXXX CMOV MOVB STORE STORE x4 MOV MOVB...
Page 178: Instruction Set Summary
User Manual C166S V2 Instruction Set Instruction Set Summary This section summarizes the instructions and lists them by functional class. This enables quick identification of the right instruction(s) for a specific function. The following notes apply to this summary: Data Addressing Modes –...
Page 179 User Manual C166S V2 Instruction Set Table 7-1 shows the various combinations of pointer post-modification for the ∗]” and “[IDX ∗]” will be addressing modes of the CoXXX instructions. The symbols “[Rw used to refer to these addressing modes. Table 7-1...
Page 180 User Manual C166S V2 Instruction Set Extension Operations The EXT* instructions override the standard DPP addressing scheme: #pag10: – Immediate 10-bit page address. #seg8: – Immediate 8-bit segment address. Branch Condition Codes Symbolically specifiable condition codes cc_UC –Unconditional cc_Z –Zero cc_NZ –Not Zero...
Page 181 User Manual C166S V2 Instruction Set Mnemonic Addressing ModesBytes Mnemonic Addressing ModesBytes ADD[B] CPL[B] ADDC[B] [Rwi] NEG[B] AND[B] [Rwi+] OR[B] #data3 DIVL SUB[B] DIVLU SUBC[B] #data16 DIVU XOR[B] MULU ASHR CMPD1/2 #data4 ROL / ROR #data4 CMPI1/2 #data16 SHL / SHR BAND bitaddrZ.z...
Page 182 User Manual C166S V2 Instruction Set Instruction Set Summary Mnemonic Description Bytes Arithmetic Operations Rw, Rw Add direct word GPR to direct GPR Rw, [Rw] Add indirect word memory to direct GPR Rw, [Rw +] Add indirect word memory to direct GPR and post-...
Page 183 User Manual C166S V2 Instruction Set Instruction Set Summary (cont’d) Mnemonic Description Bytes Arithmetic Operations (cont’d) ADDCB mem, reg Add direct byte register to direct memory with Carry Rw, Rw Subtract direct word GPR from direct GPR Rw, [Rw] Subtract indirect word memory from direct GPR...
Page 184 User Manual C166S V2 Instruction Set Instruction Set Summary (cont’d) Mnemonic Description Bytes Arithmetic Operations (cont’d) SUBCB reg, mem Subtract direct byte memory from direct register with Carry SUBCB mem, reg Subtract direct byte register from direct memory with Carry...
Page 185 User Manual C166S V2 Instruction Set Instruction Set Summary (cont’d) Mnemonic Description Bytes Logical Instructions (cont’d) Rw, Rw Bitwise OR direct word GPR with direct GPR Rw, [Rw] Bitwise OR indirect word memory with direct GPR Rw, [Rw +] Bitwise OR indirect word memory with direct GPR...
Page 186 User Manual C166S V2 Instruction Set Instruction Set Summary (cont’d) Mnemonic Description Bytes Boolean Bit Manipulation Operations BCLR bitaddr Clear direct bit BSET bitaddr Set direct bit BMOV bitaddr, bitaddr Move direct bit to direct bit BMOVN bitaddr, bitaddr Move negated direct bit to direct bit...
Page 187 User Manual C166S V2 Instruction Set Instruction Set Summary (cont’d) Mnemonic Description Bytes Compare and Loop Control Instructions (cont’d) CMPD1 Rw, mem Compare direct word memory to direct GPR and decrement GPR by 1 CMPD2 Rw, #data4 Compare immediate word data to direct GPR and...
Page 188 User Manual C166S V2 Instruction Set Instruction Set Summary (cont’d) Mnemonic Description Bytes Shift and Rotate Instructions (cont’d) Rw, #data4 Shift right direct word GPR; number of shift cycles specified by immediate data Rw, Rw Rotate left direct word GPR;...
Page 189 User Manual C166S V2 Instruction Set Instruction Set Summary (cont’d) Mnemonic Description Bytes Data Movement (cont’d) [Rw], mem Move direct word memory to indirect memory mem, [Rw] Move indirect word memory to direct memory reg, mem Move direct word memory to direct register...
Page 190 User Manual C166S V2 Instruction Set Instruction Set Summary (cont’d) Mnemonic Description Bytes Data Movement (cont’d) MOVBZ Rw, Rb Move direct byte GPR with zero extension to direct word GPR MOVBZ reg, mem Move direct byte memory with zero extension to direct...
Page 191 User Manual C166S V2 Instruction Set Instruction Set Summary (cont’d) Mnemonic Description Bytes Return Operations Return from intra-segment subroutine RETS Return from inter-segment subroutine RETP Return from intra-segment subroutine and pop direct word register from system stack RETI Return from interrupt service subroutine...
Page 192: Instruction Opcodes
User Manual C166S V2 Instruction Set Instruction Opcodes This section lists the C166S V2 CPU instructions by hexadecimal opcodes to help identify specific instructions when reading executable code, ie. during the debugging phase. Notes for Opcode Lists • These instructions are encoded by means of additional bits in the operand field of the instruction –...
Page 193 User Manual C166S V2 Instruction Set Notes on CoXXX instructions All CoXXX instructions have a 3-bit wide extended control field ’rrr’ in the operand field to control the MRW repeat counter. It is located within the CoXXX instructions at bit positions [31:29].
Page 194 User Manual C166S V2 Instruction Set Notes on the Undefined Opcodes A hardware trap occurs when one of the undefined opcodes signified by ‘----’ is decoded by the CPU. In the following table used symbols for instruction cycle times: 1 cycle, if short register addressing uses GPR...
Page 195 User Manual C166S V2 Instruction Set Hex- Bytes/ Mnemonic Operands Hex- Bytes/ Mnemonic Operands code Cycles Cycles code Rw, Rw Rw, Rw ADDB Rb, Rb SUBB Rb, Rb 4/reg reg, mem 4/reg reg, mem 4/reg ADDB reg, mem 4/reg SUBB...
Page 196 User Manual C166S V2 Instruction Set Hex- Bytes/ Mnemonic Operands Hex- Bytes/ Mnemonic Operands code Cycles code Cycles Rw, Rw Rw, Rw CMPB Rb, Rb ANDB Rb, Rb 4/reg reg, mem 4/reg reg, mem 4/reg CMPB reg, mem 4/reg ANDB...
Page 197 User Manual C166S V2 Instruction Set Hex- Bytes/ Mnemonic Operands Hex- Bytes/ Mnemonic Operands code Cycles code Cycles CMPI1 Rw, #data4 CMPD1 Rw, #data4 NEGB CMPI1 Rw, mem CMPD1 Rw, mem 4/co CoXXX 4/co CoXXX [Rw], mem MOVB [Rw], mem...
Page 198 User Manual C166S V2 Instruction Set Hex- Bytes/ Mnemonic Operands Hex- Bytes/ Mnemonic Operands code Cycles code Cycles MOVBZ Rw, Rb Rw, #data4 MOVB Rb, #data4 MOVBZ reg, mem PCALL reg, caddr CoSTORE Rw, CoREG [Rw+#data16], MOVB [Rw+#data16], MOVBZ mem, reg...
Page 199 User Manual C166S V2 Instruction Set Hex-code Extended Cycles Mnemonic Operands Hex-code CoMULu RWn, [RWm*] CoMULu RWn, [RWm*], rnd CoADD RWn, [RWm*] CoMULu- RWn, [RWm*] CoSUB RWn, [RWm*] CoMACu RWn, [RWm*] CoMACu RWn, [RWm*], rnd CoSUBR RWn, [RWm*] CoMACu- RWn, [RWm*]...
Page 200 User Manual C166S V2 Instruction Set Hex-code Extended Cycles Mnemonic Operands Hex-code CoABS RWn, [RWm*] CoMAC RWn, [RWm*] CoMAC RWn, [RWm*], rnd CoMAC- RWn, [RWm*] CoMACR RWn, [RWm*] CoMACR RWn, [RWm*], rnd CoMULu [IDXi*], [RWm*] CoMULu [IDXi*], [RWm*], rnd CoADD...
Page 201 User Manual C166S V2 Instruction Set Hex-code Extended Cycles Mnemonic Operands Hex-code CoMACMRsu [IDXi*], [RWm*], rnd CoMIN [IDXi*], [RWm*] CoMULus [IDXi*], [RWm*] CoMULus [IDXi*], [RWm*], rnd CoMULus- [IDXi*], [RWm*] CoMACus [IDXi*], [RWm*] CoMACus [IDXi*], [RWm*], rnd CoMACMus [IDXi*], [RWm*] CoMACMus...
Page 202 User Manual C166S V2 Instruction Set Hex-code Extended Cycles Mnemonic Operands Hex-code CoMAX RWn, RWm CoMULsu RWn, RWm CoMULsu RWn, RWm , rnd CoADD2 RWn, RWm CoMULsu- RWn, RWm CoSUB2 RWn, RWm CoMACsu RWn, RWm CoMACsu RWn, RWm , rnd...
Page 203 User Manual C166S V2 Instruction Set Hex-code Extended Cycles Mnemonic Operands Hex-code CoMACR RWn, RWm, rnd CoSTORE [RWn*], CoReg CoSTORE RWn, CoReg CoMOV [IDXi*], [RWm*] User Manual 7-203 V 1.7, 2001-01...
Page 204 User Manual C166S V2 Instruction Set User Manual 7-204 V 1.7, 2001-01...
Page 205: Detailed Instruction Description
All of the available addressing modes are summarized at the end of each single instruction description. In contrast to the syntax for the instructions described in the following material, the assembler provides much more flexibility in writing C166S V2 CPU programs (e.g. by generic instructions and by automatically selecting appropriate addressing modes whenever possible).
Page 206 User Manual C166S V2 Detailed Instruction Description ÿ (opX) logically COMPLEMENTED Parentheses indicate a method of addressing the used operand as follows: Specifies the immediate constant value of opX (opX) Specifies the contents of opX (opX[n]) Specifies the contents of bit n of opX...
Page 207 User Manual C166S V2 Detailed Instruction Description Data Types: This part specifies the particular data type according to the instruction. Basically, the following data types are possible: BIT, BYTE, WORD, DOUBLEWORD, ACC = 40-bit signed value Only CoXXX instructions and instructions which extend byte data to word data can change the data type.
Page 208 User Manual C166S V2 Detailed Instruction Description Condition Test Description Condition Condition Code Code Code Mnemonic Number Number cc_SLT (N⊕V) = 1 Signed less than cc_SLE (Z∨(N⊕V)) = 1 Signed less than or equal cc_SGE (N⊕V) = 0 Signed greater than or equal cc_SGT (Z∨(N⊕V)) = 0 Signed greater than...
Page 209 User Manual C166S V2 Detailed Instruction Description ’S’ The flag is set due to rules which deviate from the described standard. For more details see instruction pages (below) or the ALU status flags description. ’-’ The flag is not affected by the operation.
Page 210 User Manual C166S V2 Detailed Instruction Description 0, 1 : Constant Values :..: Each of the 4 characters immediately following a colon represents a single bit :..ii : 2-bit short GPR address (Rwi) : Code segment number :..## : 2-bit immediate constant (#irang2) :.###...
Page 211 User Manual C166S V2 Detailed Instruction Description Number of Bytes All C166S V2 CPU instructions are either 2 or 4 bytes. According to the instruction size, all instructions can be classified as either single word or double word instructions. N2N1...
Page 212: Normal Instruction Set
User Manual C166S V2 Detailed Instruction Description Normal Instruction Set Integer Addition Group Arithmetic Instructions Syntax ADD op1, op2 op1, op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ← (op1) + (op2) Description Performs a 2s complement binary addition of the source operand specified by op2 and the destination operand specified by op1.
Page 213 User Manual C166S V2 Detailed Instruction Description ADDB ADDB Integer Addition Group Arithmetic Instructions Syntax ADDB op1, op2 op1, op2 → BYTE Source Operand(s) op1 → BYTE Destination Operand(s) Operation (op1) ← (op1) + (op2) Description Performs a 2s complement binary addition of the source operand specified by op2 and the destination operand specified by op1.
Page 214 User Manual C166S V2 Detailed Instruction Description ADDC ADDC Integer Addition with Carry Group Arithmetic Instructions Syntax ADDC op1, op2 op1, op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ← (op1) + (op2) + (C) Description Performs a 2s complement binary addition of the source operand specified by op2, the destination operand specified by op1 and the previously generated carry bit.
Page 215 User Manual C166S V2 Detailed Instruction Description ADDCB ADDCB Integer Addition with Carry Group Arithmetic Instructions Syntax ADDCB op1, op2 op1, op2 → BYTE Source Operand(s) op1 → BYTE Destination Operand(s) Operation (op1) ← (op1) + (op2) + (C) Description Performs a 2s complement binary addition of the source operand specified by op2, the destination operand specified by op1 and the previously generated carry bit.
Page 216 User Manual C166S V2 Detailed Instruction Description Logical AND Group Logical Instructions Syntax AND op1, op2 op1, op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ← (op1) ∧ (op2) Description Performs a bitwise logical AND of the source operand specified by op2 and the destination operand specified by op1.
Page 217 User Manual C166S V2 Detailed Instruction Description ANDB ANDB Logical AND Group Logical Instructions Syntax ANDB op1, op2 op1, op2 → BYTE Source Operand(s) op1 → BYTE Destination Operand(s) Operation (op1) ← (op1) ∧ (op2) Description Performs a bitwise logical AND of the source operand specified by op2 and the destination operand specified by op1.
Page 218 User Manual C166S V2 Detailed Instruction Description ASHR ASHR Arithmetic Shift Right Group Shift and Rotate Instructions Syntax ASHR op1, op2 op1 → WORD Source Operand(s) op2 → shift counter op1 → WORD Destination Operand(s) Operation (count) ← (op2) (V) ← 0 (C) ←...
Page 219 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes ASHR , #data4 BC #n ASHR , Rw AC nm User Manual 8-219 V 1.7, 2001-01...
Page 220 User Manual C166S V2 Detailed Instruction Description ATOMIC ATOMIC Begin ATOMIC Sequence Group System Control Instructions Syntax ATOMIC op1 op1 → 2-bit instruction counter Source Operand(s) Destination Operand(s) none Operation (count) ← (op1) [1 ≤ ≤ Disable interrupts and Class A traps DO WHILE ((count) ≠...
Page 221 User Manual C166S V2 Detailed Instruction Description BAND BAND Bit Logical AND Group Boolean Bit Manipulation Instructions Syntax BAND op1, op2 op1, op2 → BIT Source Operand(s) op1 → BIT Destination Operand(s) Operation (op1) ← (op1) ∧ (op2) Description Performs a single bit logical AND of the source bit specified by op2 and the destination bit specified by op1.
Page 222 User Manual C166S V2 Detailed Instruction Description BCLR BCLR Bit Clear Group Boolean Bit Manipulation Instructions Syntax BCLR op1 Source Operand(s) none op1 → BIT Destination Operand(s) Operation (op1) ← 0 Description Clears the bit specified by op1. This instruction is primarily used for peripheral and system control.
Page 223 User Manual C166S V2 Detailed Instruction Description BCMP BCMP Bit to Bit Compare Group Boolean Bit Manipulation Instructions Syntax BCMP op1, op2 op1, op2 → BIT Source Operand(s) Destination Operand(s) none Operation (op1) ⇔ (op2) Description Performs a single bit comparison of the source bit specified by op1 and the source bit specified by op2.
Page 224 User Manual C166S V2 Detailed Instruction Description BFLDH BFLDH Bit Field High Byte Group Boolean Bit Manipulation Instructions Syntax BFLDH op1, op2, op3 op1 → WORD Source Operand(s) op2, op3 → BYTE op1 → WORD Destination Operand(s) Operation (count) ← 0 DO WHILE ((count) <8)
Page 225 User Manual C166S V2 Detailed Instruction Description BFLDL BFLDL Bit Field Low Byte Group Boolean Bit Manipulation Instructions Syntax BFLDL op1, op2, op3 op1 → WORD Source Operand(s) op2, op3 → BYTE op1 → WORD Destination Operand(s) Operation (count) ← 0 DO WHILE ((count) <8)
Page 226 User Manual C166S V2 Detailed Instruction Description BMOV BMOV Bit to Bit Move Group Boolean Bit Manipulation Instructions Syntax BMOV op1, op2 op2 → BIT Source Operand(s) op1 → BIT Destination Operand(s) Operation (op1) ← (op2) Description Moves a single bit from the source operand specified by op2 into the destination operand specified by op1.
Page 227 User Manual C166S V2 Detailed Instruction Description BMOVN BMOVN Bit to Bit Move and Negate Group Boolean Bit Manipulation Instructions Syntax BMOVN op1, op2 op2 → BIT Source Operand(s) op1 → BIT Destination Operand(s) Operation (op1) ← ¬(op2) Description Moves the complement of a single bit from the source operand specified by op2 into the destination operand specified by op1.
Page 228 User Manual C166S V2 Detailed Instruction Description Bit Logical OR Group Boolean Bit Manipulation Instructions Syntax BOR op1, op2 op1, op2 → BIT Source Operand(s) op1 → BIT Destination Operand(s) Operation (op1) ← (op1) ∨ (op2) Description Performs a single bit logical OR of the source bit specified by op2 and the destination bit specified by op1.
Page 229 User Manual C166S V2 Detailed Instruction Description BSET BSET Bit Set Group Boolean Bit Manipulation Instructions Syntax BSET op1 Source Operand(s) none op1 → BIT Destination Operand(s) Operation (op1) ← 1 Description Sets the bit specified by op1. CPU Flags Always cleared.
Page 230 User Manual C166S V2 Detailed Instruction Description BXOR BXOR Bit Logical XOR Group Boolean Bit Manipulation Instructions Syntax BXOR op1, op2 op1, op2 → BIT Source Operand(s) op1 → BIT Destination Operand(s) Operation (op1) ← (op1) ⊕ (op2) Description Performs a single bit logical EXCLUSIVE OR of the source bit specified by op2 and the destination bit specified by op1.
Page 231 User Manual C166S V2 Detailed Instruction Description CALLA CALLA Call Subroutine Absolute Group Call Instructions Syntax CALLA op1, op2 Alternative Syntax CALLA+ op1, op2 CALLA- op1, op2 op1 → extended condition code Source Operand(s) op2 → 16-bit address offset Destination Operand(s)
Page 232 User Manual C166S V2 Detailed Instruction Description Not affected. Encoding Mnemonic Format Bytes CALLA xcc , caddr CA d00a MM MM User Manual 8-232 V 1.7, 2001-01...
Page 233 User Manual C166S V2 Detailed Instruction Description CALLI CALLI Call Subroutine Indirect Group Call Instructions Syntax CALLI op1, op2 op1 → condition code Source Operand(s) op2 → 16-bit address offset Destination Operand(s) none Operation IF (op1) THEN (SP) ← (SP) - 2 ((SP)) ←...
Page 234 User Manual C166S V2 Detailed Instruction Description CALLR CALLR Call Subroutine Relative Group Call Instructions Syntax CALLR op1 op1 → 8-bit signed displacement Source Operand(s) Destination Operand(s) none Operation (SP) ← (SP) - 2 ((SP)) ← (IP) (IP) ← (IP) + 2*sign_extend(op1)
Page 235 User Manual C166S V2 Detailed Instruction Description CALLS CALLS Call Inter-Segment Subroutine Group Call Instructions Syntax CALLS op1, op2 op1 → segment number Source Operand(s) op2 → 16-bit address offset Destination Operand(s) none Operation (SP) ← (SP) - 2 ((SP)) ← (CSP) (SP) ←...
Page 236 User Manual C166S V2 Detailed Instruction Description Integer Compare Group Boolean Bit Manipulation Instructions Syntax CMP op1, op2 op1, op2 → WORD Source Operand(s) Destination Operand(s) none Operation (op1) ⇔ (op2) Description The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2s complement binary subtraction of op2 from op1.
Page 237 User Manual C166S V2 Detailed Instruction Description CMPB CMPB Integer Compare Group Boolean Bit Manipulation Instructions Syntax CMPB op1, op2 op1, op2 → BYTE Source Operand(s) Destination Operand(s) none Operation (op1) ⇔ (op2) Description The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2s complement binary subtraction of op2 from op1.
Page 238 User Manual C166S V2 Detailed Instruction Description CMPD1 CMPD1 Integer Compare and Decrement by 1 Group Compare and Loop Control Instructions Syntax CMPD1 op1, op2 op1, op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ⇔ (op2) (op1) ←...
Page 239 User Manual C166S V2 Detailed Instruction Description CMPD2 CMPD2 Integer Compare and Decrement by 2 Group Compare and Loop Control Instructions Syntax CMPD2 op1, op2 op1, op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ⇔ (op2) (op1) ←...
Page 240 User Manual C166S V2 Detailed Instruction Description CMPI1 CMPI1 Integer Compare and Increment by 1 Group Compare and Loop Control Instructions Syntax CMPI1 op1, op2 op1, op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ⇔ (op2) (op1) ←...
Page 241 User Manual C166S V2 Detailed Instruction Description CMPI2 CMPI2 Integer Compare and Increment by 2 Group Compare and Loop Control Instructions Syntax CMPI2 op1, op2 op1, op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ⇔ (op2) (op1) ←...
Page 242 User Manual C166S V2 Detailed Instruction Description Integer One’s Complement Group Arithmetic Instructions Syntax CPL op1 op1 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ← ¬(op1) Description Performs a 1s complement of the source operand specified by op1. The result is stored back into op1.
Page 243 User Manual C166S V2 Detailed Instruction Description CPLB CPLB Integer One’s Complement Group Arithmetic Instructions Syntax CPLB op1 op1 → BYTE Source Operand(s) op1 → BYTE Destination Operand(s) Operation (op1) ← ¬(op1) Description Performs a 1s complement of the source operand specified by op1. The result is stored back into op1.
Page 244 User Manual C166S V2 Detailed Instruction Description DISWDT DISWDT Disable Watchdog Timer Group System Control Instructions Syntax DISWDT Source Operand(s) none Destination Operand(s) none Operation Disable the watchdog timer Description This instruction disables the Watchdog Timer. If the WDTCTL bit is cleared, the DISWDT instruction can be executed at any time between the Reset and the first execution of either EINIT or SRVWDT.
Page 245 User Manual C166S V2 Detailed Instruction Description 16-by-16 Signed Division Group Arithmetic Instructions Syntax DIV op1 op1 → WORD Source Operand(s) MDL → WORD MD → DOUBLEWORD Destination Operand(s) Operation (MDL) ← (MDL) / (op1) (MDH) ← (MDL) mod (op1)
Page 246 User Manual C166S V2 Detailed Instruction Description DIVL DIVL 32-by-16 Signed Division Group Arithmetic Instructions Syntax DIVL op1 op1 → WORD Source Operand(s) MD → DOUBLEWORD MD → DOUBLEWORD Destination Operand(s) Operation (MDL) ← (MD) / (op1) (MDH) ← (MD) mod (op1)
Page 247 User Manual C166S V2 Detailed Instruction Description DIVLU DIVLU 32-by-16 Unsigned Division Group Arithmetic Instructions Syntax DIVLU op1 op1 → WORD Source Operand(s) MD → DOUBLEWORD MD → DOUBLEWORD Destination Operand(s) Operation (MDL) ← (MD) / op1 (MDH) ← (MD) mod (op1)
Page 248 User Manual C166S V2 Detailed Instruction Description DIVU DIVU 16-by-16 Unsigned Division Group Arithmetic Instructions Syntax DIVU op1 op1 → WORD Source Operand(s) MDL → WORD MD → DOUBLEWORD Destination Operand(s) Operation (MDL) ← (MDL) / (op1) (MDH) ← (MDL) mod (op1)
Page 249 User Manual C166S V2 Detailed Instruction Description EINIT EINIT End of Initialization Group System Control Instructions Syntax EINIT Source Operand(s) none Destination Operand(s) none Operation End of Initialization Description After a reset, the reset output pin RSTOUT is pulled low. It remains low until the EINIT instruction has been executed at which time it goes high.
Page 250 User Manual C166S V2 Detailed Instruction Description ENWDT ENWDT Enable Watchdog Timer Group System Control Instructions Syntax ENWDT Source Operand(s) none Destination Operand(s) none Operation Enable Watchdog Timer Description If the WDTCTL bit of the CPUCON1 register is cleared, this instruction has no effect. If the WDTCTL bit is set, this instruction enables the Watchdog Timer.
Page 251 User Manual C166S V2 Detailed Instruction Description EXTP EXTP Begin EXTended Page Sequence Group System Control Instructions Syntax EXTP op1, op2 op1 → 10-bit page number Source Operand(s) op2 → 2-bit instruction counter Destination Operand(s) none Operation (count) ← (op2) [1 ≤ op2 ≤ 4] Disable interrupts and Class A traps Data_Page ←...
Page 252 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes EXTP #pag , #irang2 D7 :01##-0 pp 0:00pp EXTP , #irang2 DC :01##-m User Manual 8-252 V 1.7, 2001-01...
Page 253 User Manual C166S V2 Detailed Instruction Description EXTPR EXTPR Begin EXTended Page and Register Sequence Group System Control Instructions Syntax EXTPR op1, op2 op1 → 10-bit page number Source Operand(s) op2 → 2-bit instruction counter Destination Operand(s) none Operation (count) ← (op2) [1 ≤ op2 ≤ 4] Disable interrupts and Class A traps Data_Page ←...
Page 254 User Manual C166S V2 Detailed Instruction Description Not affected. Not affected. Encoding Mnemonic Format Bytes EXTPR #pag , #irang2 D7 :11##-0 pp 0:00pp EXTPR , #irang2 DC :11##-m User Manual 8-254 V 1.7, 2001-01...
Page 255 User Manual C166S V2 Detailed Instruction Description EXTR EXTR Begin EXTended Register Sequence Group System Control Instructions Syntax EXTR op1 op1 → 2-bit instruction counter Source Operand(s) Destination Operand(s) none Operation (count) ← (op1) [1 ≤ op1 ≤ 4] Disable interrupts and Class A traps SFR_range ←...
Page 256 User Manual C166S V2 Detailed Instruction Description EXTS EXTS Begin EXTended Segment Sequence Group System Control Instructions Syntax EXTS op1, op2 op1 → segment number Source Operand(s) op2 → 2-bit instruction counter Destination Operand(s) none Operation (count) ← (op2) [1 ≤...
Page 257 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes EXTS #seg , #irang2 D7 :00##-0 ss 00 EXTS , #irang2 DC :00##-m User Manual 8-257 V 1.7, 2001-01...
Page 258 User Manual C166S V2 Detailed Instruction Description EXTSR EXTSR Begin EXTended Segment and Register Sequence Group System Control Instructions Syntax EXTSR op1, op2 op1 → segment number Source Operand(s) op2 → 2-bit instruction counter Destination Operand(s) none Operation (count) ← (op2) [1 ≤ op2 ≤ 4] Disable interrupts and Class A traps Data_Segment ←...
Page 259 User Manual C166S V2 Detailed Instruction Description Not affected. Not affected. Not affected. Encoding Mnemonic Format Bytes EXTSR #seg , #irang2 D7 :10##-0 ss 00 EXTSR , #irang2 DC :10##-m User Manual 8-259 V 1.7, 2001-01...
Page 260 User Manual C166S V2 Detailed Instruction Description IDLE IDLE Enter Idle Mode Group System Control Instructions Syntax IDLE Source Operand(s) none Destination Operand(s) none Operation Enter Idle Mode Description This instruction causes the part to enter the idle mode. In this mode, the CPU is powered down while the peripherals remain running.
Page 261 User Manual C166S V2 Detailed Instruction Description Relative Jump if Bit Set Group Jump Instructions Syntax JB op1, op2 op1 → BIT Source Operand(s) op2 → 8-bit signed displacement Destination Operand(s) none Operation IF ((op1) = 1) THEN (IP) ← (IP) + 2*sign_extend(op2)
Page 262 User Manual C166S V2 Detailed Instruction Description Relative Jump if Bit Set and Clear Bit Group Jump Instructions Syntax JBC op1, op2 op1 → BIT Source Operand(s) op2 → 8-bit signed displacement Destination Operand(s) none Operation IF ((op1) = 1) THEN (op1) ←...
Page 263 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes bitaddr , rel AA QQ rr q0 User Manual 8-263 V 1.7, 2001-01...
Page 264 User Manual C166S V2 Detailed Instruction Description JMPA JMPA Absolute Conditional Jump Group Jump Instructions Syntax JMPA op1, op2 Alternative Syntax JMPA+ op1, op2 JMPA- op1, op2 op1 → extended condition code Source Operand(s) op2 → 16-bit address offset Destination Operand(s)
Page 265 User Manual C166S V2 Detailed Instruction Description Not affected. Not affected. Encoding Mnemonic Format Bytes JMPA xcc , caddr EA d0la MM MM User Manual 8-265 V 1.7, 2001-01...
Page 266 User Manual C166S V2 Detailed Instruction Description JMPI JMPI Indirect Conditional Jump Group Jump Instructions Syntax JMPI op1, op2 op1 → condition code Source Operand(s) op2 → 16-bit address offset Destination Operand(s) none Operation IF ((op1) = 1) THEN (IP) ← (op2)
Page 267 User Manual C166S V2 Detailed Instruction Description JMPR JMPR Relative Conditional Jump Group Jump Instructions Syntax JMPR op1, op2 op1 → condition code Source Operand(s) op2 → 8-bit signed displacement Destination Operand(s) none Operation IF ((op1) = 1) THEN (IP) ← (IP) + 2*sign_extend(op2)
Page 268 User Manual C166S V2 Detailed Instruction Description JMPS JMPS Absolute Inter-Segment Jump Group Jump Instructions Syntax JMPS op1, op2 op1 → segment number Source Operand(s) op2 → 16-bit address offset Destination Operand(s) none Operation IF (CPUCON1.SGTDIS = 0) THEN (CSP) ← op1 END IF (IP) ←...
Page 269 User Manual C166S V2 Detailed Instruction Description Relative Jump if Bit Clear Group Jump Instructions Syntax JNB op1, op2 op1 → BIT Source Operand(s) op2 → 8-bit signed displacement Destination Operand(s) none Operation IF ((op1) = 0) THEN (IP) ← (IP) + 2*sign_extend(op2)
Page 270 User Manual C166S V2 Detailed Instruction Description JNBS JNBS Relative Jump if Bit Clear and Set Bit Group Jump Instructions Syntax JNBS op1, op2 op1 → BIT Source Operand(s) op2 → 8-bit signed displacement Destination Operand(s) none Operation IF ((op1) = 0) THEN (op1) ←...
Page 271 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes JNBS bitaddr , rel BA QQ rr q0 User Manual 8-271 V 1.7, 2001-01...
Page 272 User Manual C166S V2 Detailed Instruction Description Move Data Group Data Movement Instructions Syntax MOV op1, op2 op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ← (op2) Description Moves the contents of the source operand specified by op2 to the location specified by the destination operand op1.
Page 273 User Manual C166S V2 Detailed Instruction Description ] , Rw B8 nm +] , [Rw D8 nm ] , [Rw E8 nm ] , [Rw C8 nm ] , mem 84 0n MM MM mem , [Rw 94 0n MM MM...
Page 274 User Manual C166S V2 Detailed Instruction Description MOVB MOVB Move Data Group Data Movement Instructions Syntax MOVB op1, op2 op2 → BYTE Source Operand(s) op1 → BYTE Destination Operand(s) Operation (op1) ← (op2) Description Moves the contents of the source operand specified by op2 to the location specified by the destination operand op1.
Page 275 User Manual C166S V2 Detailed Instruction Description MOVB ] , Rb B9 nm MOVB +] , [Rw D9 nm MOVB ] , [Rw E9 nm MOVB ] , [Rw C9 nm MOVB ] , mem A4 0n MM MM MOVB...
Page 276 User Manual C166S V2 Detailed Instruction Description MOVBS MOVBS Move Byte Sign Extend Group Data Movement Instructions Syntax MOVBS op1, op2 op2 → BYTE Source Operand(s) op1 → WORD Destination Operand(s) Operation (low byte op1) ← (op2) IF ((op2[7]) = 1) THEN (high byte op1) ←...
Page 277 User Manual C166S V2 Detailed Instruction Description MOVBZ MOVBZ Move Byte Zero Extend Group Data Movement Instructions Syntax MOVBZ op1, op2 op2 → BYTE Source Operand(s) op1 → WORD Destination Operand(s) Operation (low byte op1) ← (op2) (high byte op1) ← 00H...
Page 278 User Manual C166S V2 Detailed Instruction Description Signed Multiplication Group Arithmetic Instructions Syntax MUL op1, op2 op1, op2 → WORD Source Operand(s) MD → DOUBLEWORD Destination Operand(s) Operation (MD) ← (op1) * (op2) Description Performs a 16-bit by 16-bit signed multiplication using the two words specified by operands op1 and op2 respectively.
Page 279 User Manual C166S V2 Detailed Instruction Description MULU MULU Unsigned Multiplication Group Arithmetic Instructions Syntax MULU op1, op2 op1, op2 → WORD Source Operand(s) MD → DOUBLEWORD Destination Operand(s) Operation (MD) ← (op1) * (op2) Description Performs a 16-bit by 16-bit unsigned multiplication using the two words specified by operands op1 and op2 respectively.
Page 280 User Manual C166S V2 Detailed Instruction Description Integer Two’s Complement Group Arithmetic Instructions Syntax NEG op1 op1 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ← 0 - (op1) Description Performs a binary 2s complement of the source operand specified by op1. The result is then stored in op1.
Page 281 User Manual C166S V2 Detailed Instruction Description NEGB NEGB Integer Two’s Complement Group Arithmetic Instructions Syntax NEGB op1 op1 → BYTE Source Operand(s) op1 → BYTE Destination Operand(s) Operation (op1) ← 0 - (op1) Description Performs a binary 2s complement of the source operand specified by op1. The result is then stored in op1.
Page 282 User Manual C166S V2 Detailed Instruction Description No Operation Group Null operation Syntax Source Operand(s) none Destination Operand(s) none Operation No Operation Description This instruction causes a null operation to be performed. A null operation causes no change in the status of the flags.
Page 283 User Manual C166S V2 Detailed Instruction Description Logical OR Group Logical Instructions Syntax OR op1, op2 op1, op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ← (op1) ∨ (op2) Description Performs a bitwise logical OR of the source operand specified by op2 and the destination operand specified by op1.
Page 284 User Manual C166S V2 Detailed Instruction Description Logical OR Group Logical Instructions Syntax ORB op1, op2 op1, op2 → BYTE Source Operand(s) op1 → BYTE Destination Operand(s) Operation (op1) ← (op1) ∨ (op2) Description Performs a bitwise logical OR of the source operand specified by op2 and the destination operand specified by op1.
Page 285 User Manual C166S V2 Detailed Instruction Description PCALL PCALL Push Word and Call Subroutine Absolute Group Call Instructions Syntax PCALL op1, op2 op1 → WORD Source Operand(s) op2 → 16-bit address offset Destination Operand(s) none Operation (tmp) ← (op1) (SP) ← (SP) - 2 ((SP)) ←...
Page 286 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes PCALL reg , caddr E2 RR MM MM User Manual 8-286 V 1.7, 2001-01...
Page 287 User Manual C166S V2 Detailed Instruction Description Pop Word from System Stack Group System Stack Instructions Syntax POP op1 Source Operand(s) none op1 → WORD Destination Operand(s) Operation (tmp) ← ((SP)) (SP) ← (SP) + 2 (op1) ← (tmp) Description Pops one word from the system stack specified by the Stack Pointer into the operand specified by op1.
Page 288 User Manual C166S V2 Detailed Instruction Description PRIOR PRIOR Prioritize Register Group Prioritize Instruction Syntax PRIOR op1, op2 op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (tmp) ← (op2) (count) ← 0 DO WHILE (((tmp[15]) ≠ 1) AND ((op2) ≠ 0))) (tmp[n]) ←...
Page 289 User Manual C166S V2 Detailed Instruction Description PUSH PUSH Push Word on System Stack Group System Stack Instructions Syntax PUSH op1 op1 → WORD Source Operand(s) Destination Operand(s) none Operation (tmp) ← (op1) (SP) ← (SP) - 2 ((SP)) ← (tmp)
Page 290 User Manual C166S V2 Detailed Instruction Description PWRDN PWRDN Enter Power Down Mode Group System Control Instructions Syntax PWRDN Source Operand(s) none Destination Operand(s) none Operation Enter Power Down Mode Description This instruction causes the device to enter the power down mode. In this mode, all peripherals and the CPU are powered down until the device is externally reset.
Page 291 User Manual C166S V2 Detailed Instruction Description Return from Subroutine Group Return Instructions Syntax Source Operand(s) none Destination Operand(s) none Operation (IP) ← ((SP)) (SP) ← (SP) + 2 Description Returns from a subroutine. The IP is popped from the system stack.
Page 292 User Manual C166S V2 Detailed Instruction Description RETI RETI Return from Interrupt Subroutine Group Return Instructions Syntax RETI Source Operand(s) none Destination Operand(s) none Operation (IP) ← ((SP)) (SP) ← (SP) + 2 IF (CPUCON1.SGTDIS = 0) THEN (CSP) ← ((SP)) (SP) ←...
Page 293 User Manual C166S V2 Detailed Instruction Description RETP RETP Return from Subroutine and Pop Word Group Return Instructions Syntax RETP op1 Source Operand(s) none op1 → WORD Destination Operand(s) Operation (IP) ← ((SP)) (SP) ← (SP) + 2 (tmp) ← ((SP)) (SP) ←...
Page 294 User Manual C166S V2 Detailed Instruction Description RETS RETS Return from Inter-Segment Subroutine Group Return Instructions Syntax RETS Source Operand(s) none Destination Operand(s) none Operation (IP) ← ((SP)) (SP) ← (SP) + 2 IF (CPUCON1.SGTDIS = 0) THEN (CSP) ← ((SP)) END IF (SP) ←...
Page 295 User Manual C166S V2 Detailed Instruction Description Rotate Left Group Shift and Rotate Instructions Syntax ROL op1, op2 op1 → WORD Source Operand(s) op2 → shift counter op1 → WORD Destination Operand(s) Operation (count) ← (op2) (C) ← 0 DO WHILE ((count) ≠ 0) (C) ←...
Page 296 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes , #data4 1C #n , Rw 0C nm User Manual 8-296 V 1.7, 2001-01...
Page 297 User Manual C166S V2 Detailed Instruction Description Rotate Right Group Shift and Rotate Instructions Syntax ROR op1, op2 op1 → WORD Source Operand(s) op2 → shift counter op1 → WORD Destination Operand(s) Operation (count) ← (op2) (C) ← 0 (V) ← 0 DO WHILE ((count) ≠...
Page 298 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes , #data4 3C #n , Rw 2C nm User Manual 8-298 V 1.7, 2001-01...
Page 299 User Manual C166S V2 Detailed Instruction Description SBRK SBRK Software Break Group System Control Instructions Syntax SBRK Source Operand(s) none Destination Operand(s) none Operation Software Break Description If the SBRK instruction is enabled by the One Chip Emulator (OCE), then the break mode is activated.
Page 300 User Manual C166S V2 Detailed Instruction Description SCXT SCXT Switch Context Group System Stack Instructions Syntax SCXT op1, op2 op1, op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (tmp1) ← (op1) (tmp2) ← (op2) (SP) ← (SP) - 2 ((SP)) ←...
Page 301 User Manual C166S V2 Detailed Instruction Description Shift Left Group Shift and Rotate Instructions Syntax SHL op1, op2 op1 → WORD Source Operand(s) op2 → shift counter op1 → WORD Destination Operand(s) Operation (count) ← (op2) (C) ← 0 DO WHILE ((count) ≠ 0) (C) ←...
Page 302 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes , #data4 5C #n , Rw 4C nm User Manual 8-302 V 1.7, 2001-01...
Page 303 User Manual C166S V2 Detailed Instruction Description Shift Right Group Shift and Rotate Instructions Syntax SHR op1, op2 op1 → WORD Source Operand(s) op2 → shift counter op1 → WORD Destination Operand(s) Operation (count) ← (op2) (C) ← 0 (V) ← 0 DO WHILE ((count) ≠...
Page 304 User Manual C166S V2 Detailed Instruction Description The carry flag is set according to the last least significant bit shifted out of op1. Cleared for a shift count of zero. Set if the most significant bit of the result is set. Cleared otherwise.
Page 305 User Manual C166S V2 Detailed Instruction Description SRST SRST Software Reset Group System Control Instructions Syntax SRST Source Operand(s) none Destination Operand(s) none Operation Software Reset Description This instruction is used to perform a software reset. A software reset has the same effect on the microcontroller as an externally applied hardware reset.
Page 306 User Manual C166S V2 Detailed Instruction Description SRVWDT SRVWDT Service Watchdog Timer Group System Control Instructions Syntax SRVWDT Source Operand(s) none Destination Operand(s) none Operation Service Watchdog Timer Description This instruction reloads the high order byte of the Watchdog Timer with a preset value and clears the low byte.
Page 307 User Manual C166S V2 Detailed Instruction Description Integer Subtraction Group Arithmetic Instructions Syntax SUB op1, op2 op1, op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ← (op1) - (op2) Description Performs a 2s complement binary subtraction of the source operand specified by op2 and the destination operand specified by op1.
Page 308 User Manual C166S V2 Detailed Instruction Description SUBB SUBB Integer Subtraction Group Arithmetic Instructions Syntax SUBB op1, op2 op1, op2 → BYTE Source Operand(s) op1 → BYTE Destination Operand(s) Operation (op1) ← (op1) - (op2) Description Performs a 2s complement binary subtraction of the source operand specified by op2 and the destination operand specified by op1.
Page 309 User Manual C166S V2 Detailed Instruction Description SUBC SUBC Integer Subtraction with Carry Group Arithmetic Instructions Syntax SUBC op1, op2 op1, op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ← (op1) - (op2) - (C) Description Performs a 2s complement binary subtraction of the source operand specified by op2 and the previously generated carry bit from the destination operand specified by op1.
Page 310 User Manual C166S V2 Detailed Instruction Description SUBCB SUBCB Integer Subtraction with Carry Group Arithmetic Instructions Syntax SUBCB op1, op2 op1, op2 → BYTE Source Operand(s) op1 → BYTE Destination Operand(s) Operation (op1) ← (op1) - (op2) - (C) Description Performs a 2s complement binary subtraction of the source operand specified by op2 and the previously generated carry bit from the destination operand specified by op1.
Page 311 User Manual C166S V2 Detailed Instruction Description TRAP TRAP Software Trap Group Call Instructions Syntax TRAP op1 op1 → 7-bit trap number Source Operand(s) Destination Operand(s) none Operation (SP) ← (SP) - 2 ((SP) ← (PSW) IF (CPUCON1.SGTDIS = 0) THEN (SP) ←...
Page 312 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes TRAP #trap7 9B t:ttt0 User Manual 8-312 V 1.7, 2001-01...
Page 313 User Manual C166S V2 Detailed Instruction Description Logical Exclusive OR Group Logical Instructions Syntax XOR op1, op2 op1, op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ← (op1) ⊕ (op2) Description Performs a bitwise logical EXCLUSIVE OR of the source operand specified by op2 and the destination operand specified by op1.
Page 314 User Manual C166S V2 Detailed Instruction Description XORB XORB Logical Exclusive OR Group Logical Instructions Syntax XORB op1, op2 op1, op2 → BYTE Source Operand(s) op1 → BYTE Destination Operand(s) Operation (op1) ← (op1) ⊕ (op2) Description Performs a bitwise logical EXCLUSIVE OR of the source operand specified by op2 and the destination operand specified by op1.
Page 315: Dsp Instruction Set
User Manual C166S V2 Detailed Instruction Description DSP Instruction Set User Manual 8-315 V 1.7, 2001-01...
Page 316 User Manual C166S V2 Detailed Instruction Description CoABS CoABS Absolute Value Group Arithmetic Instructions Syntax CoABS ACC → 40-bit signed value Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (ACC) ← Abs(ACC) Description Computes the absolute value of the 40-bit ACC contents.
Page 317 User Manual C166S V2 Detailed Instruction Description CoABS CoABS Absolute Value Group Arithmetic Instructions Syntax CoABS op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (ACC) ← Abs((op2) || (op1)) Description Computes the absolute value of a 40-bit source operand and loads the result in the 40-bit ACC register.
Page 318 User Manual C166S V2 Detailed Instruction Description CoADD CoADD Group Arithmetic Instructions Syntax CoADD op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← (op2) || (op1) (ACC) ← (ACC) + (tmp)
Page 319 User Manual C166S V2 Detailed Instruction Description CoADD2 CoADD2 Group Arithmetic Instructions Syntax CoADD2 op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← 2 * ((op2) || (op1)) (ACC) ← (ACC) + (tmp)
Page 320 User Manual C166S V2 Detailed Instruction Description CoASHR CoASHR Accumulator Arithmetic Shift Right with Round Group Shift Instructions Syntax CoASHR op1, rnd op1 → shift counter Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (count) ← (op1) (C) ← 0 DO WHILE (count) ≠...
Page 321 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes CoASHR #data5 , rnd A3 00 B2 rrr#:# CoASHR , rnd A3 nn BA rrr0:0000 CoASHR *] , rnd 83 mm BA rrr0:0qqq User Manual 8-321 V 1.7, 2001-01...
Page 322 User Manual C166S V2 Detailed Instruction Description CoASHR CoASHR Accumulator Arithmetic Shift Right Group Shift Instructions Syntax CoASHR op1 op1 → shift counter Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (count) ← (op1) (C) ← 0 DO WHILE (count) ≠ 0 (ACC[n]) ←...
Page 323 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes CoASHR #data5 A3 00 A2 rrr#:# CoASHR A3 nn AA rrr0:0000 CoASHR 83 mm AA rrr0:0qqq User Manual 8-323 V 1.7, 2001-01...
Page 324 User Manual C166S V2 Detailed Instruction Description CoCMP CoCMP Compare Group Compare Instructions Syntax CoCMP op1, op2 op1, op2 → WORD Source Operand(s) Destination Operand(s) none Operation tmp ← (op2) || (op1) (ACC) ⇔ (tmp) Description Subtracts a 40-bit signed operand from the 40-bit ACC contents and updates the N, Z and C flags of the MSW register leaving the ACC register unchanged.
Page 325 User Manual C166S V2 Detailed Instruction Description CoLOAD CoLOAD Load Accumulator Group Arithmetic Instructions Syntax CoLOAD op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← (op2) || (op1) (ACC) ← 0 + (tmp) Description Loads the 40-bit ACC register with a 40-bit source operand.
Page 326 User Manual C166S V2 Detailed Instruction Description CoLOAD- CoLOAD- Load Accumulator Group Arithmetic Instructions Syntax CoLOAD- op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← (op2) || (op1) (ACC) ← 0 - (tmp) Description Loads the 40-bit ACC register with a 40-bit source operand.
Page 327 User Manual C166S V2 Detailed Instruction Description CoLOAD2 CoLOAD2 Load Accumulator Group Arithmetic Instructions Syntax CoLOAD2 op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← 2 * ((op2) || (op1) ) (ACC) ←...
Page 328 User Manual C166S V2 Detailed Instruction Description CoLOAD2- CoLOAD2- Load Accumulator Group Arithmetic Instructions Syntax CoLOAD2- op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← 2 * ((op2) || (op1) ) (ACC) ←...
Page 329 User Manual C166S V2 Detailed Instruction Description CoMAC CoMAC Multiply-Accumulate with Round Group Multiply/Multiply-Accumulate Instructions Syntax CoMAC op1, op2, rnd op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation IF (MP = 1) THEN (tmp) ← ((op1) * (op2)) <<1 (ACC) ←...
Page 330 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes CoMAC , Rw , rnd A3 nm D1 rrr0:0000 CoMAC , [Rw *] , rnd 83 nm D1 rrr0:0qqq CoMAC [IDXi*] , [Rw *] , rnd 93 Xm D1 rrr0:0qqq...
Page 331 User Manual C166S V2 Detailed Instruction Description CoMAC CoMAC Multiply-Accumulate Group Multiply/Multiply-Accumulate Instructions Syntax CoMAC op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation IF (MP = 1) THEN (tmp) ← ((op1) * (op2)) <<1 (ACC) ←...
Page 332 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes CoMAC , Rw A3 nm D0 rrr0:0000 CoMAC , [Rw 83 nm D0 rrr0:0qqq CoMAC [IDXi*] , [Rw 93 Xm D0 rrr0:0qqq User Manual 8-332 V 1.7, 2001-01...
Page 333 User Manual C166S V2 Detailed Instruction Description CoMAC- CoMAC- Multiply-Accumulate Group Multiply/Multiply-Accumulate Instructions Syntax CoMAC- op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation IF (MP = 1) THEN (tmp) ← ((op1) * (op2)) <<1 (ACC) ←...
Page 334 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes CoMAC- , Rw A3 nm E0 rrr0:0000 CoMAC- , [Rw 83 nm E0 rrr0:0qqq CoMAC- [IDXi*] , [Rw 93 Xm E0 rrr0:0qqq User Manual 8-334 V 1.7, 2001-01...
Page 335 User Manual C166S V2 Detailed Instruction Description CoMACM CoMACM Multiply-Accumulate & Move & Round Group Multiply/Multiply-Accumulate Instructions Syntax CoMACM op1, op2, rnd op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation IF (MP = 1) THEN (tmp) ←...
Page 336 User Manual C166S V2 Detailed Instruction Description Set if the most significant bit of the result is set. Cleared otherwise. Encoding Mnemonic Format Bytes CoMACM [IDXi*], [Rw *] , rnd 93 Xm D9 rrr0:0qqq User Manual 8-336 V 1.7, 2001-01...
Page 337 User Manual C166S V2 Detailed Instruction Description CoMACM CoMACM Multiply-Accumulate & Move Group Multiply/Multiply-Accumulate Instructions Syntax CoMACM op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation IF (MP = 1) THEN (tmp) ← (((op1)) * ((op2))) <<1 (ACC) ←...
Page 338 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes CoMACM [IDXi*], [Rw 93 Xm D8 rrr0:0qqq User Manual 8-338 V 1.7, 2001-01...
Page 339 User Manual C166S V2 Detailed Instruction Description CoMACM- CoMACM- Multiply-Accumulate & Move Group Multiply/Multiply-Accumulate Instructions Syntax CoMACM- op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation IF (MP = 1) THEN (tmp) ← (((op1)) * ((op2))) <<1 (ACC) ←...
Page 340 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes CoMACM- [IDXi*], [Rw 93 Xm E8 rrr0:0qqq User Manual 8-340 V 1.7, 2001-01...
Page 341 User Manual C166S V2 Detailed Instruction Description CoMACMR CoMACMR Multiply-Accumulate & Move & Round Group Multiply/Multiply-Accumulate Instructions Syntax CoMACMR op1, op2, rnd op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation IF (MP = 1) THEN (tmp) ←...
Page 342 User Manual C166S V2 Detailed Instruction Description Set if result equals zero. Cleared otherwise. Set if the most significant bit of the result is set. Cleared otherwise. Encoding Mnemonic Format Bytes CoMACMR [IDXi*], [Rw *] , rnd 93 Xm F9 rrr0:0qqq...
Page 343 User Manual C166S V2 Detailed Instruction Description CoMACMR CoMACMR Multiply-Accumulate & Move Group Multiply/Multiply-Accumulate Instructions Syntax CoMACMR op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation IF (MP = 1) THEN (tmp) ← (((op1)) * ((op2))) <<1 (ACC) ←...
Page 344 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes CoMACMR [IDXi*], [Rw 93 Xm F8 rrr0:0qqq User Manual 8-344 V 1.7, 2001-01...
Page 345 User Manual C166S V2 Detailed Instruction Description CoMACMRsu CoMACMRsu Multiply-Accumulate & Move & Round Group Multiply/Multiply-Accumulate Instructions Syntax CoMACMRsu op1, op2, rnd op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← ((op1)) * ((op2)) (ACC) ←...
Page 346 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes CoMACMRsu [IDXi*], [Rw *] , rnd 93 Xm 79 rrr0:0qqq User Manual 8-346 V 1.7, 2001-01...
Page 347 User Manual C166S V2 Detailed Instruction Description CoMACMRsu CoMACMRsu Multiply-Accumulate & Move Group Multiply/Multiply-Accumulate Instructions Syntax CoMACMRsu op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← ((op1)) * ((op2)) (ACC) ← (tmp) - (ACC) ((IDXi(-*))) ←...
Page 348 User Manual C166S V2 Detailed Instruction Description CoMACMRu CoMACMRu Multiply-Accumulate & Move & Round Group Multiply/Multiply-Accumulate Instructions Syntax CoMACMRu op1, op2, rnd op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← ((op1))*((op2)) (ACC) ← (tmp) - (ACC) + 00 0000 8000h (MAL) ←...
Page 349 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes CoMACMRu [IDXi*], [Rw *] , rnd 93 Xm 39 rrr0:0qqq User Manual 8-349 V 1.7, 2001-01...
Page 350 User Manual C166S V2 Detailed Instruction Description CoMACMRu CoMACMRu Multiply-Accumulate & Move Group Multiply/Multiply-Accumulate Instructions Syntax CoMACMRu op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← ((op1))*((op2)) (ACC) ← (tmp) - (ACC) ((IDXi(-*))) ←...
Page 351 User Manual C166S V2 Detailed Instruction Description CoMACMRus CoMACMRus Multiply-Accumulate & Move & Round Group Multiply/Multiply-Accumulate Instructions Syntax CoMACMRus op1, op2, rnd op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← ((op1)) * ((op2)) (ACC) ←...
Page 352 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes CoMACMRus [IDXi*], [Rw *] , rnd 93 Xm B9 rrr0:0qqq User Manual 8-352 V 1.7, 2001-01...
Page 353 User Manual C166S V2 Detailed Instruction Description CoMACMRus CoMACMRus Multiply-Accumulate & Move Group Multiply/Multiply-Accumulate Instructions Syntax CoMACMRus op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← ((op1)) * ((op2)) (ACC) ← (tmp) - (ACC) ((IDXi(-*))) ←...
Page 354 User Manual C166S V2 Detailed Instruction Description CoMACMsu CoMACMsu Multiply-Accumulate & Move & Round Group Multiply/Multiply-Accumulate Instructions Syntax CoMACMsu op1, op2, rnd op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← ((op1)) * ((op2)) (ACC) ←...
Page 355 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes CoMACMsu [IDXi*], [Rw *] , rnd 93 Xm 59 rrr0:0qqq User Manual 8-355 V 1.7, 2001-01...
Page 356 User Manual C166S V2 Detailed Instruction Description CoMACMsu CoMACMsu Multiply-Accumulate & Move Group Multiply/Multiply-Accumulate Instructions Syntax CoMACMsu op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← ((op1)) * ((op2)) (ACC) ← (ACC) + (tmp) ((IDXi(-*))) ←...
Page 357 User Manual C166S V2 Detailed Instruction Description CoMACMsu- CoMACMsu- Multiply-Accumulate & Move Group Multiply/Multiply-Accumulate Instructions Syntax CoMACMsu- op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← ((op1)) * ((op2)) (ACC) ← (ACC) - (tmp) ((IDXi(-*))) ←...
Page 358 User Manual C166S V2 Detailed Instruction Description CoMACMu CoMACMu Multiply-Accumulate & Move & Round Group Multiply/Multiply-Accumulate Instructions Syntax CoMACMu op1, op2, rnd op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← ((op1))*((op2)) (ACC) ← (ACC) + (tmp) + 00 0000 8000h (MAL) ←...
Page 359 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes CoMACMu [IDXi*], [Rw *] , rnd 93 Xm 19 rrr0:0qqq User Manual 8-359 V 1.7, 2001-01...
Page 360 User Manual C166S V2 Detailed Instruction Description CoMACMu CoMACMu Multiply-Accumulate & Move Group Multiply/Multiply-Accumulate Instructions Syntax CoMACMu op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← ((op1))*((op2)) (ACC) ← (ACC) + (tmp) ((IDXi(-*))) ←...
Page 361 User Manual C166S V2 Detailed Instruction Description CoMACMu- CoMACMu- Multiply-Accumulate & Move Group Multiply/Multiply-Accumulate Instructions Syntax CoMACMu- op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← ((op1))*((op2)) (ACC) ← (ACC) - (tmp) ((IDXi(-*))) ←...
Page 362 User Manual C166S V2 Detailed Instruction Description CoMACMus CoMACMus Multiply-Accumulate & Move & Round Group Multiply/Multiply-Accumulate Instructions Syntax CoMACMus op1, op2, rnd op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← ((op1)) * ((op2)) (ACC) ←...
Page 363 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes CoMACMus [IDXi*], [Rw *] , rnd 93 Xm 99 rrr0:0qqq User Manual 8-363 V 1.7, 2001-01...
Page 364 User Manual C166S V2 Detailed Instruction Description CoMACMus CoMACMus Multiply-Accumulate & Move Group Multiply/Multiply-Accumulate Instructions Syntax CoMACMus op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← ((op1)) * ((op2)) (ACC) ← (ACC) + (tmp) ((IDXi(-*))) ←...
Page 365 User Manual C166S V2 Detailed Instruction Description CoMACMus- CoMACMus- Multiply-Accumulate & Move Group Multiply/Multiply-Accumulate Instructions Syntax CoMACMus- op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← ((op1)) * ((op2)) (ACC) ← (ACC) - (tmp) ((IDXi(-*))) ←...
Page 366 User Manual C166S V2 Detailed Instruction Description CoMACR CoMACR Multiply-Accumulate & Round Group Multiply/Multiply-Accumulate Instructions Syntax CoMACR op1, op2, rnd op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation IF (MP = 1) THEN (tmp) ← ((op1) * (op2)) <<1 (ACC) ←...
Page 367 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes CoMACR , Rw , rnd A3 nm F1 rrr0:0000 CoMACR , [Rw *] , rnd 83 nm F1 rrr0:0qqq CoMACR [IDXi*] , [Rw *] , rnd 93 Xm F1 rrr0:0qqq...
Page 368 User Manual C166S V2 Detailed Instruction Description CoMACR CoMACR Multiply-Accumulate Group Multiply/Multiply-Accumulate Instructions Syntax CoMACR op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation IF (MP = 1) THEN (tmp) ← ((op1) * (op2)) <<1 (ACC) ←...
Page 369 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes CoMACR , Rw A3 nm F0 rrr0:0000 CoMACR , [Rw 83 nm F0 rrr0:0qqq CoMACR [IDXi*] , [Rw 93 Xm F0 rrr0:0qqq User Manual 8-369 V 1.7, 2001-01...
Page 370 User Manual C166S V2 Detailed Instruction Description CoMACRsu CoMACRsu Mixed Multiply-Accumulate & Round Group Multiply/Multiply-Accumulate Instructions Syntax CoMACRsu op1, op2, rnd op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← (op1) * (op2) (ACC) ←...
Page 371 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes CoMACRsu , Rw , rnd A3 nm 71 rrr0:0000 CoMACRsu , [Rw *] , rnd 83 nm 71 rrr0:0qqq CoMACRsu [IDXi*] , [Rw *] , rnd 93 Xm 71 rrr0:0qqq...
Page 372 User Manual C166S V2 Detailed Instruction Description CoMACRsu CoMACRsu Mixed Multiply-Accumulate Group Multiply/Multiply-Accumulate Instructions Syntax CoMACRsu op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← (op1) * (op2) (ACC) ← (tmp) - (ACC)
Page 373 User Manual C166S V2 Detailed Instruction Description CoMACRu CoMACRu Unsigned Multiply-Accumulate & Round Group Multiply/Multiply-Accumulate Instructions Syntax CoMACRu op1, op2, rnd op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← (op1) * (op2) (ACC) ←...
Page 374 User Manual C166S V2 Detailed Instruction Description CoMACRu CoMACRu Unsigned Multiply-Accumulate Group Multiply/Multiply-Accumulate Instructions Syntax CoMACRu op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← (op1) * (op2) (ACC) ← (tmp) - (ACC) Description Multiplies the two unsigned 16-bit source operands op1 and op2.
Page 375 User Manual C166S V2 Detailed Instruction Description CoMACRus CoMACRus Mixed Multiply-Accumulate & Round Group Multiply/Multiply-Accumulate Instructions Syntax CoMACRus op1, op2, rnd op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← (op1) * (op2) (ACC) ←...
Page 376 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes CoMACRus , Rw , rnd A3 nm B1 rrr0:0000 CoMACRus , [Rw *] , rnd 83 nm B1 rrr0:0qqq CoMACRus [IDXi*] , [Rw *] , rnd 93 Xm B1 rrr0:0qqq...
Page 377 User Manual C166S V2 Detailed Instruction Description CoMACRus CoMACRus Mixed Multiply-Accumulate Group Multiply/Multiply-Accumulate Instructions Syntax CoMACRus op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← (op1) * (op2) (ACC) ← (tmp) - (ACC)
Page 378 User Manual C166S V2 Detailed Instruction Description CoMACsu CoMACsu Mixed Multiply-Accumulate & Round Group Multiply/Multiply-Accumulate Instructions Syntax CoMACsu op1, op2, rnd op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← (op1) * (op2) (ACC) ←...
Page 379 User Manual C166S V2 Detailed Instruction Description CoMACsu CoMACsu Mixed Multiply-Accumulate Group Multiply/Multiply-Accumulate Instructions Syntax CoMACsu op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← (op1) * (op2) (ACC) ← (ACC) + (tmp)
Page 380 User Manual C166S V2 Detailed Instruction Description CoMACsu- CoMACsu- Mixed Multiply-Accumulate Group Multiply/Multiply-Accumulate Instructions Syntax CoMACsu- op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← (op1) * (op2) (ACC) ← (ACC) - (tmp)
Page 381 User Manual C166S V2 Detailed Instruction Description CoMACu CoMACu Unsigned Multiply-Accumulate & Round Group Multiply/Multiply-Accumulate Instructions Syntax CoMACu op1, op2, rnd op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← (op1) * (op2) (ACC) ←...
Page 382 User Manual C166S V2 Detailed Instruction Description CoMACu CoMACu Unsigned Multiply-Accumulate Group Multiply/Multiply-Accumulate Instructions Syntax CoMACu op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← (op1) * (op2) (ACC) ← (ACC) + (tmp) Description Multiplies the two unsigned 16-bit source operands op1 and op2.
Page 383 User Manual C166S V2 Detailed Instruction Description CoMACu- CoMACu- Unsigned Multiply-Accumulate Group Multiply/Multiply-Accumulate Instructions Syntax CoMACu- op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← (op1) * (op2) (ACC) ← (ACC) - (tmp) Description Multiplies the two unsigned 16-bit source operands op1 and op2.
Page 384 User Manual C166S V2 Detailed Instruction Description CoMACus CoMACus Mixed Multiply-Accumulate with Round Group Multiply/Multiply-Accumulate Instructions Syntax CoMACus op1, op2, rnd op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← (op1) * (op2) (ACC) ←...
Page 385 User Manual C166S V2 Detailed Instruction Description CoMACus CoMACus Mixed Multiply-Accumulate Group Multiply/Multiply-Accumulate Instructions Syntax CoMACus op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← (op1) * (op2) (ACC) ← (ACC) + (tmp)
Page 386 User Manual C166S V2 Detailed Instruction Description CoMACus- CoMACus- Mixed Multiply-Accumulate Group Multiply/Multiply-Accumulate Instructions Syntax CoMACus- op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← (op1) * (op2) (ACC) ← (ACC) - (tmp)
Page 387 User Manual C166S V2 Detailed Instruction Description CoMAX CoMAX Maximum Group Compare Instructions Syntax CoMAX op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← (op2) || (op1) (ACC) ← max((ACC),(tmp)) Description Compares a signed 40-bit operand against the 40-bit ACC register contents.
Page 388 User Manual C166S V2 Detailed Instruction Description CoMIN CoMIN Minimum Group Compare Instructions Syntax CoMIN op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← (op2) || (op1) (ACC) ← min((ACC),(tmp)) Description Compares a signed 40-bit operand against the 40-bit ACC register contents.
Page 389 User Manual C166S V2 Detailed Instruction Description CoMOV CoMOV Memory to Memory Move Group Data Movement Instructions Syntax CoMOV op1, op2 op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ← (op2) Description Moves the contents of the memory location specified by the source operand op2 to the memory location specified by the destination operand op1.
Page 390 User Manual C166S V2 Detailed Instruction Description CoMUL CoMUL Signed Multiply with Round Group Multiply/Multiply-Accumulate Instructions Syntax CoMUL op1, op2, rnd op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation IF (MP = 1) THEN (ACC) ←...
Page 391 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes CoMUL , Rw , rnd A3 nm C1 rrr0:0000 CoMUL , [Rw *] , rnd 83 nm C1 rrr0:0qqq CoMUL [IDXi*] , [Rw *] , rnd 93 Xm C1 rrr0:0qqq...
Page 392 User Manual C166S V2 Detailed Instruction Description CoMUL CoMUL Signed Multiply Group Multiply/Multiply-Accumulate Instructions Syntax CoMUL op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation IF (MP = 1) THEN (ACC) ← ((op1) * (op2)) <<1 ELSE (ACC) ←...
Page 393 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes CoMUL , Rw A3 nm C0 rrr0:0000 CoMUL , [Rw 83 nm C0 rrr0:0qqq CoMUL [IDXi*] , [Rw 93 Xm C0 rrr0:0qqq User Manual 8-393 V 1.7, 2001-01...
Page 394 User Manual C166S V2 Detailed Instruction Description CoMUL- CoMUL- Signed Multiply Group Multiply/Multiply-Accumulate Instructions Syntax CoMUL- op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation IF (MP = 1) THEN (ACC) ← - ((op1) * (op2)) <<1 ELSE (ACC) ←...
Page 395 User Manual C166S V2 Detailed Instruction Description CoMULsu CoMULsu Mixed Multiply & Round Group Multiply/Multiply-Accumulate Instructions Syntax CoMULsu op1, op2, rnd op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (ACC) ← (op1) * (op2) + 00 0000 8000h (MAL) ←...
Page 396 User Manual C166S V2 Detailed Instruction Description CoMULsu CoMULsu Mixed Multiply Group Multiply/Multiply-Accumulate Instructions Syntax CoMULsu op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (ACC) ← (op1) * (op2) Description Multiplies the two signed and unsigned 16-bit source operands op1 and op2, respectively.
Page 397 User Manual C166S V2 Detailed Instruction Description CoMULsu- CoMULsu- Mixed Multiply Group Multiply/Multiply-Accumulate Instructions Syntax CoMULsu- op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (ACC) ← - ((op1) * (op2)) Description Multiplies the two signed and unsigned 16-bit source operands op1 and op2, respectively.
Page 398 User Manual C166S V2 Detailed Instruction Description CoMULu CoMULu Unsigned Multiply with Round Group Multiply/Multiply-Accumulate Instructions Syntax CoMULu op1, op2, rnd op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (ACC) ← (op1) * (op2) + 00 0000 8000h (MAL) ←...
Page 399 User Manual C166S V2 Detailed Instruction Description CoMULu CoMULu Unsigned Multiply Group Multiply/Multiply-Accumulate Instructions Syntax CoMULu op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (ACC) ← (op1) * (op2) Description Multiplies the two unsigned 16-bit source operands op1 and op2. The resulting unsigned 32-bit product is zero-extended before being stored in the 40-bit ACC register.
Page 400 User Manual C166S V2 Detailed Instruction Description CoMULu- CoMULu- Unsigned Multiply Group Multiply/Multiply-Accumulate Instructions Syntax CoMULu- op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (ACC) ← - ((op1) * (op2)) Description Multiplies the two unsigned 16-bit source operands op1 and op2. The resulting unsigned 32-bit product is first zero-extended;...
Page 401 User Manual C166S V2 Detailed Instruction Description CoMULus CoMULus Mixed Multiply with Round Group Multiply/Multiply-Accumulate Instructions Syntax CoMULus op1, op2, rnd op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (ACC) ← (op1) * (op2) + 00 0000 8000h (MAL) ←...
Page 402 User Manual C166S V2 Detailed Instruction Description CoMULus CoMULus Mixed Multiply Group Multiply/Multiply-Accumulate Instructions Syntax CoMULus op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (ACC) ← (op1) * (op2) Description Multiplies the two unsigned and signed 16-bit source operands op1 and op2, respectively.
Page 403 User Manual C166S V2 Detailed Instruction Description CoMULus- CoMULus- Mixed Multiply Group Multiply/Multiply-Accumulate Instructions Syntax CoMULus- op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (ACC) ← - ((op1) * (op2)) Description Multiplies the two unsigned and signed 16-bit source operands op1 and op2, respectively.
Page 404 User Manual C166S V2 Detailed Instruction Description CoNEG CoNEG Negate Accumulator Group Arithmetic Instructions Syntax CoNEG ACC → 40-bit signed value Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (ACC) ← 0 - (ACC) Description The ACC register contents are subtracted from zero before being stored in the 40-bit ACC register.
Page 405 User Manual C166S V2 Detailed Instruction Description CoNEG CoNEG Negate Accumulator with Round Group Arithmetic Instructions Syntax CoNEG rnd ACC → 40-bit signed value Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (ACC) ← 0 - (ACC) + 00 0000 8000h (MAL) ←...
Page 406 User Manual C166S V2 Detailed Instruction Description CoNOP CoNOP No-Operation Group Arithmetic Instructions Syntax CoNOP Source Operand(s) none Destination Operand(s) none Operation No Operation Description Modifies the address pointers. MAC Flags Sat. Not affected. Not affected. Not affected. MSV Not affected.
Page 407 User Manual C166S V2 Detailed Instruction Description CoRND CoRND Round Accumulator Group Shift Instructions Syntax CoRND ACC → 40-bit signed value Source Operand(s) ACC → 40-bit signed value signed value Destination Operand(s) Operation (ACC) ← (ACC) + 00 0000 8000h (MAL) ←...
Page 408 User Manual C166S V2 Detailed Instruction Description CoSHL CoSHL Accumulator Logical Shift Left Group Shift Instructions Syntax CoSHL op1 op1 → 5-bit unsigned data Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (count) ← (op1) (C) <- (ACC[39]) DO WHILE ((count) ≠...
Page 409 User Manual C166S V2 Detailed Instruction Description Set if the most significant bit of the result is set. Cleared otherwise. Encoding Mnemonic Format Bytes CoSHL #data5 A3 00 82 rrr#:# CoSHL A3 nn 8A rrr0:0000 CoSHL 83 mm 8A rrr0:0qqq...
Page 410 User Manual C166S V2 Detailed Instruction Description CoSHR CoSHR Accumulator Logical Shift Right Group Shift Instructions Syntax CoSHR op1 op1 → 5-bit unsigned data Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (count) ← (op1) (C) ← 0 DO WHILE (count) ≠...
Page 411 User Manual C166S V2 Detailed Instruction Description Encoding Mnemonic Format Bytes CoSHR #data5 A3 00 92 rrr#:# CoSHR A3 nn 9A rrr0:0000 CoSHR 83 mm 9A rrr0:0qqq User Manual 8-411 V 1.7, 2001-01...
Page 412 User Manual C166S V2 Detailed Instruction Description CoSTORE CoSTORE Store a MAC-Unit Register Group Data Movement Instructions Syntax CoSTORE op1, op2 op2 → WORD Source Operand(s) op1 → WORD Destination Operand(s) Operation (op1) ← (op2) Description Moves the contents of a MAC-Unit register specified by the source operand op2 to the location specified by the destination operand op1.
Page 413 User Manual C166S V2 Detailed Instruction Description CoSUB CoSUB Subtract Group Arithmetic Instructions Syntax CoSUB op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← (op2) || (op1) (ACC) ← (ACC) - (tmp)
Page 414 User Manual C166S V2 Detailed Instruction Description CoSUB2 CoSUB2 Subtract Group Arithmetic Instructions Syntax CoSUB2 op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← 2 * (op2) || (op1) (ACC) ← (ACC) - (tmp)
Page 415 User Manual C166S V2 Detailed Instruction Description CoSUB2R CoSUB2R Subtract Group Arithmetic Instructions Syntax CoSUB2R op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← 2 * (op2) || (op1) (ACC) ← (tmp) - (ACC)
Page 416 User Manual C166S V2 Detailed Instruction Description CoSUBR CoSUBR Subtract Group Arithmetic Instructions Syntax CoSUBR op1, op2 op1, op2 → WORD Source Operand(s) ACC → 40-bit signed value Destination Operand(s) Operation (tmp) ← (op2) || (op1) (ACC) ← (tmp) - (ACC)
Page 417: Instructions For Ocds/Itc Injection And System Control
User Manual C166S V2 Detailed Instruction Description Instructions for OCDS/ITC injection and System Control The following table gives a brief overview of the instructions that are defined especially for injections via the Interrupt and PEC controller and for debugging reasons by the OCDS.
Page 418 User Manual C166S V2 Detailed Instruction Description Mnemonic Operands Opcode Cycle Comment OLOADB mem24 2D MM reads byte from memory and writes to OCDS OSTOREB mem24 3D MM reads byte from OCDS and writes to memory OLOAD Rx, #banksel2 4D ss00:x 00 00...
Page 419 User Manual C166S V2 Detailed Instruction Description Mnemonic Operands Opcode Cycle Comment mem24 CD MM word PEC transfer started by ITC DPEC mem24 DD MM word PEC transfer started by OCDS PECB mem24 AD MM byte PEC transfer started by ITC...
Page 420 User Manual C166S V2 Detailed Instruction Description User Manual 8-420 V 1.7, 2001-01...
Page 421: Summary Of Cpu/Subsystem Registers
CSFRs are the control registers of the C166S V2 CPU. The register set for the PEC and Interrupt Controller is listed. For easy reference, the SFRs are ordered in two different ways: •...
Page 422 User Manual C166S V2 Summary of CPU/Subsystem Registers The first 8 GPRs (R7...R0) may be also accessed bytewise. Unlike SFRs, writing to a GPR byte does not affect another byte of the GPR. The following byte-accessible registers have special names.
Page 423: Core Special Function Registers
Ordered by Name Table 9-3 lists all CSFRs implemented in the C166S V2 CPU, in alphabetical order. Bit addressable CSFRs are marked with the letter “b” in the “Name” column. CSFRs within the Extended CSFR-Space (ECSFRs) are marked with the letter “E” in the “8-Bit Address”...
Page 424: Ordered By Address
Ordered by Address Table 9-4 lists all CSFRs implemented in the C166S V2 ordered by physical address. Bit addressable CSFRs are marked with the letter “b” in the “Name” column. CSFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in the “8-Bit Address”...
Page 425 User Manual C166S V2 Summary of CPU/Subsystem Registers Table 9-4 Addressing Modes to Access Core-SFRs: Ordered by Address Name Physical 8-Bit Description Reset Address Address Value FE08 Code Segment Pointer 0000 (8 bits, not directly writable) FE0C Multiply Divide Register – High Word...
Page 426: Register Overview Interrupt And Peripheral Event Controller
9.3.1 Ordered by Name Table 9-5 lists all xSFRs that are implemented in the C166S V2 Interrupt and Peripheral Event Controller, ordered by name. Bit addressable SFRs are marked with the letter “b” in the “Name” column. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in the “8-Bit Address”...
Page 427: Ordered By Address
9.3.2 Ordered by Address Table 9-6 lists all xSFRs that are implemented in the C166S V2 Interrupt and Peripheral Event Controller ordered by address. Bit addressable SFRs are marked with the letter “b” in the “Name” column. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in the “8-Bit Address”...
Page 428 User Manual C166S V2 Summary of CPU/Subsystem Registers Table 9-6 Register Overview Interrupt and PEC: Ordered by Address Name Physical 8-bit Description Reset Address Address Value FINT0CSP EC00 Fast Interrupt 0 CSP Register 0000 FINT0ADDR EC02 Fast Interrupt 0 Address Register...
Page 429 User Manual C166S V2 Summary of CPU/Subsystem Registers Table 9-6 Register Overview Interrupt and PEC: Ordered by Address (cont’d) Name Physical 8-bit Description Reset Address Address Value PECSEG5 EC8A PEC Pointer 5 Segment Address Reg. 0000 PECSEG6 EC8C PEC Pointer 6 Segment Address Reg. 0000...
Page 430: Register Overview External Bus Controller
User Manual C166S V2 Summary of CPU/Subsystem Registers Register Overview External Bus Controller 9.4.1 Ordered by Name Table 9-7 Register Overview EBC: Ordered by Name Name Physical 8-Bit Description Reset Address Address Value ADDRSEL1 EE1E Address Window Selection for CS1...
Page 431: Ordered By Address
User Manual C166S V2 Summary of CPU/Subsystem Registers 9.4.2 Ordered by Address Table 9-8 Register Overview EBC: Ordered by Name Name Physical 8-Bit Description Reset Address Address Value EBCMOD0 EE00 Alternate Function of EBC Pins 00F0 EBCMOD1 EE02 Global Behavior of EBC...
Page 432 User Manual C166S V2 Summary of CPU/Subsystem Registers User Manual 9-432 V 1.7, 2001-01...
Page 433: Keyword Index
Keyword Index Keyword Index This section lists a number of keywords which refer to specific details of the C166S V2 in terms of its architecture, its functional units or functions. This helps to quickly find the answer to specific questions about the C166S V2.
Page 434 User Manual C166S V2 Keyword Index BOR 228 CoMACu- 383 BSET 229 CoMACus 384, 385 BXOR 230 CoMACus- 386 CALLA 231 CoMAX 387 CALLI 233 CoMIN 388 CALLR 234 CoMOV 389 CALLS 235 CoMUL 390, 392 CMP 236 CoMUL- 394...
Page 435 User Manual C166S V2 Keyword Index JMPR 267 JMPS 268 JTAG 13 JNB 269 JNBS 270 MOV 272 MAH Register 423, 425 MOVB 274 MAL Register 423, 425 MOVBS 276 MCW Register 423, 425 MOVBZ 277 MDC Register 423, 425...
Page 436 User Manual C166S V2 Keyword Index SP Register 424, 425 SPSEG Register 424, 425 Register STKOV Register 424, 425 CP 423, 425 STKUN Register 424, 425 CPUCON1 423, 425 System Control Unit 13 CPUCON2 423, 425 CPUID 423, 424 CSP 423, 425...
Page 438 Dr. Ulrich Schumacher h t t p : / / w w w . i n f i n e o n . c o m Published by Infineon Technologies AG...
Page 439 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Infineon SAFXC164CS16F40FBB SAF-XC164CS-16F40F BB SAK-XC164CS-16F20F BB SAK-XC164CS-16F40F BB SAF- XC164CS-16F20F BB FX164CS16F40FBBXP XC164CS16F40FBBFXUMA1 XC164CS16F40FBBKXUMA1 XC164CS16F40FBBFXQMA1...

Infineon Technologies C166S V2 User Manual

1 Introduction

2 Central Processing Unit

3 C166S V2 Memory Organization

4 Instruction Pipeline

5 Interrupt and Exception Handling

6 External Bus Controller

7 Instruction Set

8 Detailed Instruction Description

9 Summary of Cpu/Subsystem Registers

10 Keyword Index

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