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15.2
BMU Features
The BMU implements the following features:
•
Fully synchronous module running at the Peripheral Bus clock frequency
•
Implements a standard interrupt service node connecting to the TriCore and PCP
interrupt busses.
– Every internal interrupt source can be identified by a dedicated status flag, cleared
by software only. New interrupt events with an active status flag do not lead to a
new interrupt.
•
Logs write transactions to software selectable peripheral address space
– Uses the System-on-chip Address decoders select lines to qualify target
peripherals (no internal address space decoding)
•
Implements a Bus Transaction Fifo (BTF) that can be accessed via the FPI slave
interface using BTR2, BTR4 or BTR8 FPI read bursts. The size of the BTF can be
configured on a product basis. It must be a power of two in size.
– The BTF entries are protected by Error Correction Codes (ECC) with single-bit
error correction and double-bit error detection capability (SECDED) covering the
data field.
– The BTF is accessed as a cyclic buffer with automatic wrap around support. The
BTF write and read pointers are controlled by Hardware.
•
The BTF entries are made of the following FPI information:
– FPI_A[27:2] address bits of the FPI transaction.
– FPI_SVM FPI supervisor mode indication
– FPI_TAG[3:0] FPI TAG, identifies the FPI bus master
– FPI_STATUS Transaction completion status. This is not an FPI signal
– FPI_D[31:0] FPI write data
•
Fifo Handler that monitors the fullness of the BTF:
– implements a configurable threshold register to early detect fullness threshold.
– detects and prevents overruns and underruns (configurable).
•
The BTF can be used as a standard memory mapped SRAM in non-safety
applications. The SRAM can only be accessed using BTR2, BTR4 or BTR8 FPI
bursts.
User's Manual
BMU, V2.6
15-3
TC1728
Bus Monitor Unit (BMU)
V1.0, 2011-12
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