Revision History - Infineon Technologies TC1728 User Manual

15.7

Revision History

Table 15-7 Revision history
Date Description
Version 2.5 -> version 2.6
30.09.2009 - Described limitations on the usage pf the
Version 2.4 -> version 2.5
09.09.2009 - SIST mode is only possible when the BMU is configured in
SRAM mode (see
Version 2.3 -> version 2.4
31.08.2009 - Added MIECON and MIECON2 registers and related
description in new
- Added input pin secwen_i
- Fixes according to RT #764: BMU_CLC.DISS BPI Register
Accesses
- Fixes according to RT #7630 Ticket: precise logging
behavior when switching from disabled state to enabled
state in
Version 2.1 -> version 2.2
16.07.2009 - Fixes according to RT #7327 Ticket: SHE master filtering
- Fixes according to RT #7325 Ticket: removed redundant
SRC register description
- Fixes according to RT #7301 Ticket: described data
storage in SRAM mode and address alignment restrictions
- Removed bit fields in the CLC register controlling the
suspend and sleep modes as their are not supported.
Version 2.0 -> version 2.1
User's Manual
BMU, V2.6
CTL register description)
Memory Integrity Error Control
CLC register section.
15-50
Bus Monitor Unit (BMU)
Name
CTL register A. Vilela
A. Vilela
A. Vilela
section.
A. Vilela
V1.0, 2011-12
TC1728