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13.2.1.2 Request Set and Clear Bits (SETR, CLRR)
The SETR and CLRR bits allow software to set or clear the service request bit SRR.
Writing a 1 to SETR causes bit SRR to be set to 1. Writing a 1 to CLRR causes bit SRR
to be cleared to 0. If hardware attempts to modify SRR during a read-modify-write
software operation (such as the bit-set or bit-clear instructions), the software operation
will succeed and the hardware operation will have no effect.
The value written to SETR or CLRR is not stored. Writing a 0 to these bits has no effect.
These bits always return 0 when read. If both, SETR and CLRR, are set to 1 at the same
time, SRR is not changed.
13.2.1.3 Enable Bit (SRE)
The SRE bit enables an interrupt to take part in the arbitration for the selected service
provider. It does not enable or disable the setting of the request flag SRR; the request
flag can be set by hardware or by software (via SETR) independent of the state of the
SRE bit. This allows service requests to be handled automatically by hardware or
through software polling.
If SRE = 1, pending service requests are passed on to the designated service provider
for interrupt arbitration. The SRR bit is automatically set to 0 by hardware when the
service request is acknowledged and serviced. It is recommended that in this case,
software should not modify the SRR bit to avoid unexpected behavior due to the
hardware controlling this bit.
If SRE = 0, pending service requests are not passed on to service providers. Software
can poll the SRR bit to check whether a service request is pending. To acknowledge the
service request, the SRR bit must then be reset by software by writing a 1 to CLRR.
Note: In this document, 'active source' means an SRN whose Service Request Control
Register has its request enable bit SRE set to 1 to allow its service requests to
participate in interrupt arbitration.
13.2.1.4 Service Request Flag (SRR)
When set, the SRR flag indicates that a service request is pending. It can be set or reset
directly by hardware or indirectly through software using the SETR and CLRR bits.
Writing directly to this bit via software has no effect.
The SRR status bit can be directly set or reset by the associated hardware. For instance,
in the General Purpose Array Unit, an associated timer event can cause this bit to be set
to 1. The details of how hardware events can cause the SRR bit to be set are defined in
the individual peripheral/module chapters.
The acknowledgment of the service request by either the Interrupt Control Unit (ICU) or
the PCP Interrupt Control Unit (PICU) causes the SRR bit to be cleared.
User's Manual
Interrupt, V1.4
13-5
TC1728
Interrupt System
V1.0, 2011-12
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