Infineon Technologies TC1728 User Manual page 1276

Field Bits
CLKCTRL 8
CSL [10:9]
CSH [12:11] rw
CSC [14:13] rw
User's Manual
MSC, V1.37 2009-05
Type Description
rw Clock Control
This bit determines the activation of clock output
FCL.
0 FCL is activated only during the active phases
B
of data or command frames (not during
passive time frames).
1 FCL is always active whether or not a
B
downstream frame is currently transmitted.
rw Chip Enable Selection for ENL
This bit field selects the chip enable output ENx that
becomes active during the SRL active phase
(ENL = 1) of a data frame. The active level of ENx is
defined by bit CSLP.
00 EN0 line is selected for ENL.
B
01 EN1 line is selected for ENL.
B
10 EN2 line is selected for ENL.
B
11 EN3 line is selected for ENL.
B
Chip Enable Selection for ENH
This bit field selects the chip enable output ENx that
becomes active during the SRH active phase
(ENH = 1) of a data frame. The active level of ENx is
defined by bit CSLP.
00 EN0 line is selected for ENH.
B
01 EN1 line is selected for ENH.
B
10 EN2 line is selected for ENH.
B
11 EN3 line is selected for ENH.
B
Chip Enable Selection for ENC
This bit field selects the chip enable output ENx that
becomes active during the active phase (ENC = 1) of
a command frame. The active level of ENx is defined
by bit CSLP.
00 EN0 line is selected for ENC.
B
01 EN1 line is selected for ENC.
B
10 EN2 line is selected for ENC.
B
11 EN3 line is selected for ENC.
B
19-57
Micro Second Channel (MSC)
TC1728
V1.0, 2011-12