Infineon Technologies C166S V2 Manuals

Manuals and User Guides for Infineon Technologies C166S V2. We have 1 Infineon Technologies C166S V2 manual available for free PDF download: User Manual

Infineon Technologies C166S V2 User Manual

Infineon Technologies C166S V2 User Manual (439 pages)

16-Bit Microcontroller

Brand: Infineon Technologies | Category: Microcontrollers | Size: 2.97 MB

Table of Contents

Table of Contents
5
1 Introduction

9
- Technical Overview
  9
- System Description
  10
- Cpu
  11
- On-Chip Memory Modules
  12
- Data Management Unit (DMU)
  12
- Program Memory Unit (PMU)
  12
- Interrupt and PEC Controller
  13
- OCDS and JTAG
  13
- External Bus Controller (EBC)
  13
- System Control Unit (SCU)
  13
- Clock Generation Unit (CGU)
  14
- On-Chip Bootstrap Loader
  14
2 Central Processing Unit

15
3 C166S V2 Memory Organization

91
- Data Organization in Memory
  93
- Internal Program Memory
  93
- DPRAM, Internal SRAM, and SFR Areas
  94
- Data Memories
  94
- Special Function Register Areas
  96
- IO Area
  97
- PEC Source and Destination Pointers
  97
- External Memory Space
  98
- Boot and Debug/Monitor Program Memories
  98
- Crossing Memory Boundaries
  99
- System Stack
  99
- Data Organization in Global General Purpose Registers
  100
4 Instruction Pipeline

103
- Instruction Dependencies in Different Pipeline Stages
  104
- The General Purpose Registers
  104
- Indirect Addressing Modes
  106
- Memory Bandwidth Conflicts
  107
- CPU-Sfrs and the Pipeline
  110
5 Interrupt and Exception Handling

117
- Interrupt System and Control
  118
- General Interrupt System Structure
  118
- Interrupt Arbitration
  120
- Interrupt Control
  122
- Interrupt Vector Table
  124
- Interrupt Jump Table Cache
  125
- Status and Switch Context Control
  127
- Interrupt Control Functions in the PSW
  127
- Saving the Status During Interrupt Service
  129
- Context Switching
  130
- Fast Bank Switching
  131
- Traps
  132
- Software Traps
  132
- Hardware Traps
  133
- Peripheral Event Controller
  138
- PEC Control Registers
  139
- The PEC Source and Destination Pointer
  145
- PEC Handler Interrupt Actions Summary
  147
- PEC Channel Assignment and Arbitration
  149
- CPU Action Control Unit
  151
6 External Bus Controller

153
- Introduction
  153
- Timing Principles
  154
- A Phase
  157
- B Phase
  157
- C Phase
  157
- D Phase
  157
- E Phase
  157
- F Phase
  158
- Functional Description
  158
- Configuration Register Overview
  158
- The EBC MODE Registers Ebcmodx
  158
- The Timing Configuration Registers Tconcsx
  161
- The Function Configuration Registers Fconcsx
  163
- The Address Window Selection Registers Addrselx
  164
- Definition of Address Areas
  164
- Address Window Arbitration
  166
- Ready Controlled Bus Cycles
  167
- General
  167
- The Synchronous/Asynchronous READY
  168
- Combining the READY Function with Predefined Wait States
  168
- EBC Idle State
  169
- Multi Master Systems
  169
- External Bus Arbitration
  169
- Initialization of Arbitration
  169
- Arbitration Master Scheme
  170
- Arbitration Slave Scheme
  171
- Locking the Bus
  171
- Connecting Multimaster Systems
  172
- Fastest Possible External Access
  173
7 Instruction Set

175
- Short Instruction Summary
  175
- Instruction Set Summary
  178
- Instruction Opcodes
  192
8 Detailed Instruction Description

205
9 Summary of Cpu/Subsystem Registers

421
- General Purpose Registers (Gprs)
  421
- Core Special Function Registers
  423
- Ordered by Name
  423
- Ordered by Address
  424
- Register Overview Interrupt and Peripheral Event Controller
  426
- Ordered by Name
  426
- Ordered by Address
  427
- Register Overview External Bus Controller
  430
- Ordered by Name
  430
- Ordered by Address
  431
10 Keyword Index

433

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