Infineon Technologies TC1728 User Manual page 1359

The Module Control Register MCR contains basic settings that determine the operation
of the MultiCAN module.
The write access to the lowest byte of the MCR register is possible only if the CCE bits
of all CAN nodes are set (NCRx.CCE bits). The NCRx.INIT bits will be automatically set
when the lowest byte of the MCR register is written, independent of the setting of the
CCE bits. The INIT bits have to be reset by software in order to activate the CAN nodes.
The reconfiguration of the clock source has to be done by using two writes: first a write
of zero to the CLKSEL bitfield, and then a second write defining the new clock source.
Between the first and the second write a delay of minimum 4 * (1/
be inserted by software, where
Exception: in case that the
(MCR.CLKSEL = 1), no delay cycles between the writes are necessary. In both cases,
simply using one write defining the new clock source is not allowed.
Note: If the baude rate logic is supplied from an unstable clock source, or no clock at all,
the CAN functionality is not guaranteed.
MCR
Module Control Register
31 30 29 28
15 14 13 12
MPSEL
rw
Field Bits
CLKSEL [3:0]
User's Manual
MultiCAN, V2.24
Controller Area Network Controller (MultiCAN)
f
is the frequency being switched off with the first write.
A
f
is selected as a baud rate and bit timing logic clock
CLC
(1C8
27 26 25 24
11 10 9 8
Type Description
rw Baud Rate Logic Clock Select
0000 No clock supplied
B
f
0001
B
0010 Oscillator Clock
B
0100 E-Ray PLL clock
B
1000 hard wired to 0
B
... not allowed
B
20-66
)
H
23 22 21
0
r
7 6 5
0
r
CLC
TC1728
f ) + 2 * (1/ f
A CLC
Reset Value: 0000 0000
20 19 18 17
4 3 2 1
CLKSEL
rw
V1.0, 2011-12
) must
H
16
0