Interrupt System Registers - Infineon Technologies TC1728 User Manual

15.6.6

Interrupt System Registers

SRC
Service Request Control Register
31 30 29 28
15 14 13 12
SET CLR
SRR SRE
R R
w w rwh rw
Field Bits
SRPN [7:0]
TOS 10
SRE 12
SRR 13
CLRR 14
User's Manual
BMU, V2.6
(FC
27 26 25 24
11 10 9 8
0 TOS 0
r rw r
Type Description
rw Service Request Priority Number
00 Service request is never serviced
H
01 Service request is on lowest priority
H
...
FF Service request is on highest priority
H
rw Type of Service Control
0 CPU service is initiated
B
1 PCP service is initiated
B
rw Service Request Enable
0 Service request is disabled
B
1 Service request is enabled
B
rwh Service Request Flag
0 No service request is pending
B
1 A service request is pending
B
w Request Clear Bit
CLRR is required to clear SRR.
0 No action
B
1 Clear SRR; bit value is not stored; read always
B
returns 0; no action if SETR is set also.
15-48
) Reset Value: 0000 0000
H
23 22 21
0
r
7 6 5
TC1728
Bus Monitor Unit (BMU)
20 19 18 17
4 3 2 1
SRPN
rw
1)
V1.0, 2011-12
H
16
0