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18.1.1
Overview
The SSC supports full-duplex and half-duplex serial synchronous communication up to
55.0 Mbit/s (@ 110.0 MHz module clock, Master Mode). The serial clock signal can be
generated by the SSC itself (Master Mode) or can be received from an external master
(Slave Mode). Data width, shift direction, clock polarity and phase are programmable.
This allows communication with SPI-compatible devices. Transmission and reception of
data is double-buffered. A shift clock generator provides the SSC with a separate serial
clock signal. Seven slave select inputs are available for Slave Mode operation. Eight
programmable slave select outputs (chip selects) are supported in Master Mode.
Features:
•
Master and Slave Mode operation
– Full-duplex or half-duplex operation
– Automatic pad control possible
•
Flexible data format
– Programmable number of data bits: 2 to 16 data bits (with parity: 1 to 15 data bits)
– Programmable shift direction: LSB or MSB shift first
– Programmable clock polarity: Idle low or idle high state for the shift clock
– Programmable clock/data phase: Data shift with leading or trailing edge of the shift
clock
•
Baud rate generation
– Master Mode: 55.0 Mbit/s to 839.3 bit/s (@ 110 MHz module clock)
– Slave Mode: 27.5 Mbit/s to 839.3 bit/s (@ 110 MHz module clock)
•
Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error, parity error)
•
Queued SSC Mode supports control and data handling by the DMA controller
•
Flexible SSC pin configuration
•
Hardware supported parity mode
– Individually selectable for transmit and receive frames
– Even/odd parity selection
•
Seven slave select inputs SLSI[7:1] in Slave Mode
•
Eight programmable slave select outputs SLSO[7:0] in Master Mode
– Automatic SLSO generation with programmable timing
– Programmable active level and enable control
– Combinable with SLSO output signals from other SSC modules
User's Manual
SSC, V1.41 2010-06
Synchronous Serial Interface (SSC)
18-2
TC1728
V1.0, 2011-12
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