Infineon Technologies TC1728 User Manual page 1270

Field Bits
RDIE [15:14]
0 6, 10,
[31:16]
User's Manual
MSC, V1.37 2009-05
Type Description
rw Receive Data Interrupt Enable
This bit field determines the enable conditions for the
receive data interrupt.
00 Interrupt generation disabled.
B
01 An interrupt is generated when data is received
B
and written into the upstream data registers
UDx (x = 0-3).
10 An interrupt is generated as with RDIE = 01
B
but only if the received data is not equal to 00
11 An interrupt is generated when data is received
B
and written into register UD3.
r Reserved
Read as 0; should be written with 0.
19-51
Micro Second Channel (MSC)
TC1728
B
.
H
V1.0, 2011-12