Infineon Technologies TC1728 User Manual

32-bit single-chip microcontroller

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TC1728

32-Bit Single-Chip Microcontroller

User's Manual

V1.0 2011-12

M i c r o c o n t r o l l e r s

Table of Contents

Summary of Contents for Infineon Technologies TC1728

Page 1 TC1728 32-Bit Single-Chip Microcontroller User’s Manual V1.0 2011-12 M i c r o c o n t r o l l e r s...
Page 2 Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life.
Page 3 TC1728 32-Bit Single-Chip Microcontroller User’s Manual V1.0 2011-12 M i c r o c o n t r o l l e r s...
Page 4 Trademarks ® TriCore is a trademark of Infineon Technologies AG. We Listen to Your Comments Is there any information in this document that you feel is wrong, unclear or missing? Your feedback will help us to continuously improve the quality of this document.
Page 5: Table Of Contents
TC1728 Block Diagram ........1-8...
Page 6 TC1728 Table of Contents 2.5.1 Registers ..........2-18 CPU General Purpose Registers .
Page 7 TC1728 Table of Contents 3.1.1 Clock Generation Unit ........3-4 3.1.1.1...
Page 8 TC1728 Table of Contents 3.3.2.8 External Request Unit Registers ......3-99 Power Supply and Control ........3-115 3.4.1...
Page 9 TC1728 Table of Contents 3.12.1 GPTA Input IN1 Control ........3-179 3.12.2...
Page 10 TC1728 Table of Contents 4.6.3.4 Combination of Triggers ....... . 4-42 4.6.3.5...
Page 11 TC1728 Table of Contents 5.6.5.1 Read Protection ........5-64 5.6.5.2...
Page 12 TC1728 Table of Contents 7.1.4.1 Header Check in Alternate Boot Modes ....7-10 7.1.5 Startup Errors Handling ........7-12 Bootstrap Loaders .
Page 13 TC1728 Table of Contents 9.6.3.2 Port 2 Output Modification Register ......9-43 9.6.3.3 Port 2 Input/Output Control Register 12 ....9-44 9.6.3.4...
Page 14 TC1728 Table of Contents 9.12.1 Port 9 Configuration ........9-76 9.12.2...
Page 15 TC1728 Table of Contents 10.4 PCP Programming Model ........10-8 10.4.1...
Page 16 TC1728 Table of Contents 10.9.1.1 Enforced PRAM Partitioning ......10-44 10.9.1.2 Protected Channel PRAM ......10-45 10.9.2...
Page 17 TC1728 Table of Contents 10.17.13 Memory Integrity Error Status Register for CMEM, PCP_MIESTATC ..10-86 10.17.14 Register Protection Register, PCP_RPROT ....10-87 10.17.15...
Page 18 Implementing Multiply Algorithms ......10-157 10.22 Implementation of the PCP in the TC1728 ....10-159 10.22.1 PCP Memories .
Page 19 TC1728 Table of Contents 11.2.4.1 Shadowed Source or Destination Address ....11-7 11.2.4.2 DMA Channel Request Control ......11-11 11.2.4.3...
Page 20 Interrupt Vector Table ........13-15 13.8 Usage of the TC1728 Interrupt System ......13-18 13.8.1 Spanning Interrupt Service Routines Across Vector Entries .
Page 21 TC1728 Table of Contents 13.8.4 Splitting Interrupt Service Across Different Priority Levels ..13-20 13.8.5 Using different Priorities for the same Interrupt Source ..13-21 13.8.6...
Page 22 TC1728 Table of Contents 15.6.4 BMU: Fifo Monitoring Registers ......15-42 15.6.5 BMU: SIST Mode Access Control Register ....15-45 15.6.6...
Page 23 TC1728 Table of Contents 17.1.7 Interrupts ..........17-19 17.2...
Page 24 TC1728 Table of Contents 19.1 MSC Kernel Description ........19-3 19.1.1...
Page 25 TC1728 Table of Contents 20.1 CAN Basics ..........20-2 20.1.1...
Page 26 TC1728 Table of Contents 20.3.11.4 Message Object FIFO Structure ......20-49 20.3.11.5 Receive FIFO ........20-51 20.3.11.6...
Page 27 TC1728 Table of Contents 21.5.2.10 Output Buffer ........21-180 21.6...
Page 28 TC1728 Table of Contents 21.6.8.5 NULL Frame Transmission ......21-229 21.6.9 Receive Process ........21-230 21.6.9.1...
Page 29 TC1728 Table of Contents 22.1.1.2 Naming Conventions ........22-4 22.1.1.3...
Page 30 Receiver Interrupt Registers ......22-120 22.5 Implementation of the MLI0 in TC1728 ..... . . 22-127 22.5.1 Interfaces of the MLI Modules .
Page 31 TC1728 Table of Contents 23.1 What is new? ..........23-1 ®...
Page 32 TC1728 Table of Contents 23.4.8 Global Timer Cell Registers ......23-184 23.4.9...
Page 33 TC1728 Table of Contents 24.2.8 T12 related Registers ........24-35 24.2.8.1...
Page 34 TC1728 Table of Contents 24.9.2.3 Status Reset Register ....... . 24-105 24.9.2.4...
Page 35 TC1728 Table of Contents 25.3 Miscellaneous Registers ........25-68 25.4...
Page 36 TC1728 Table of Contents 26.2.9.1 Overview ......... . . 26-52 26.2.9.2...
Page 37 Implementation ......... 26-139 26.3.1 Request Sources in TC1728 ......26-139 26.3.2 Address Map .
Page 38 TC1728 Table of Contents 27.2.9 Calibration ..........27-21 27.2.9.1...
Page 39: Introduction
This TC1728 User’s Manual describes the features of the TC1728 with respect to the TriCore Architecture. Where the TC1728 directly implements TriCore architectural functions, this manual simply refers to those functions as features of the TC1728. In all cases where this manual describes a TC1728 feature without referring to the TriCore Architecture, this means that the TC1728 is a direct implementation of the TriCore Architecture.
Page 40 TC1728 Introduction Current CPU Priority Number bit field CPU_ICR.CCPN is cleared”. Most of the register names contain a module name prefix, separated by an underscore character “_” from the actual register name (for example, “ASC0_CON”, where “ASC0” is the module name prefix, and “CON” is the kernel register name). In chapters describing the kernels of the peripheral modules, the registers are mainly referenced with their kernel register names.
Page 41: Reserved, Undefined, And Unimplemented Terminology
TC1728 Introduction 1.1.3 Reserved, Undefined, and Unimplemented Terminology In tables where register bit fields are defined, the following conventions are used to indicate undefined and unimplemented function. Furthermore, types of bits and bit fields are defined using the abbreviations as shown in Table 1-1.
Page 42: Abbreviations And Acronyms
TC1728 Introduction Table 1-2 Access Terms Symbol Description Access Mode: Access permitted in User Mode 0 or 1. Reset Value: Value or bit is not changed by a reset operation. Access permitted in Supervisor Mode. Read-only register. Only 32-bit word accesses are permitted to this register/address range.
Page 43 TC1728 Introduction Cyclic Redundancy Code Context Save Area CSFR Core Special Function Register Device Access Port Device Access Server DCACHE Data Cache DFLASH Data Flash Memory DGPR Data General Purpose Register Direct Memory Access Data Memory Interface Error Correction Code...
Page 44 TC1728 Introduction Most Significant Bit Micro Second Channel Not Connected Non-Maskable Interrupt OCDS On-Chip Debug Support OVRAM Overlay Memory Peripheral Control Processor Program Memory Unit Phase Locked Loop PFLASH Program Flash Memory Program Memory Interface Program Memory Unit PRAM PCP Parameter RAM...
Page 45: System Architecture Of The Tc1728
Analog-to-Digital converters. Within the TC1728, all these peripheral units are connected to the TriCore CPU/system via the Flexible Peripheral Interconnect (FPI) Bus and the Local Memory Bus (LMB). Several I/O lines on the TC1728 ports are reserved for these peripheral units to communicate with the external world.
Page 46: Tc1728 Block Diagram
TC1728 Introduction 1.2.1 TC1728 Block Diagram Figure 1-1 shows the block diagram of the TC1728. Please note that not all features that are shown in the block diagram are available in the other package variants. Abbreviations: ICACHE: Instruction Cache DCACHE...
Page 47: System Features
TC1728 Introduction 1.2.2 System Features The TC1728 has the following features: Packages • PG-LQFP-176 package (TC1728) • PG-LQFP-144 package (TC1724) User’s Manual V1.0, 2011-12 Intro, V1.0...
Page 48: Cpu Cores Of The Tc1728
TC1728 Introduction 1.2.3 CPU Cores of the TC1728 The TC1728 includes a high Performance CPU and a Peripheral Control Processor. 1.2.3.1 High-performance 32-bit CPU This chapter gives an overview about the TriCore 1 architecture. TriCore (TC1.3.1) Architectural Highlights • Unified RISC MCU/DSP •...
Page 49: High-Performance 32-Bit Peripheral Control Processor
TC1728 Introduction – 0 Kbyte Data Cache (DACHE) • On-chip SRAMs with ECC protection 1.2.3.2 High-performance 32-bit Peripheral Control Processor The PCP is a flexible Peripheral Control Processor optimized for interrupt handling and thus unloading the CPU. Features • Data move between any two memory or I/O locations •...
Page 50: On-Chip System Units
DMA controller, embedded Flash module, Flexible CRC Engine, System Timer Unit, System Control Unit, Overlay Control module, interrupt system and ports. 1.3.1 Flexible Interrupt System The TC1728 includes a programmable interrupt system with the following features: Features • Fast interrupt response •...
Page 51: System Timer
TC1728 Introduction 1.3.2 System Timer The TC1728’s STM is designed for global system timing applications requiring both high precision and long range. Features • Free-running 56-bit counter • All 56 bits can be read synchronously • Different 32-bit portions of the 56-bit counter can be read synchronously •...
Page 52: System Control Unit
Double Reset Detection: If a Watchdog induced reset occurs twice, a severe system malfunction is assumed and the TC1728 is held in reset until a System Reset occurs. This prevents the device from being periodically reset if, for instance, connection to...
Page 53: External Interface
Flexible Peripheral Interconnect Buses (FPI Bus) for on-chip interconnections and its FPI Bus control unit (SBCU) • The System Timer (STM) with high-precision, long-range timing capabilities • The TC1728 includes a power management system, a watchdog timer as well as reset logic User’s Manual 1-15 V1.0, 2011-12...
Page 54: Cpu Subsystem
TC1728 CPU Subsystem CPU Subsystem The TC1728 processor contains a TriCore 1.3.1 CPU. This chapter describes the implementation-specific options of the CPU, and should be read in conjunction with the TriCore Architecture Manual, which describes the complete TriCore Architecture including the register and instruction set.
Page 55: Central Processing Unit Features
TC1728 CPU Subsystem Central Processing Unit Features The 133MHz TriCore TC1728 CPU includes: Architecture • 32-bit load store architecture • 4 Gbyte address range (2 • 16-bit and 32-bit instructions for reduced code size • Data types: – Boolean, integer with saturation, bit array, signed fraction, character, double-word integers, signed integer, unsigned integer, IEEE-754 single-precision floating point •...
Page 56: Cpu Diagram
TC1728 CPU Subsystem 2.2.1 CPU Diagram The Central Processing Unit (CPU) comprises of an Instruction Fetch Unit, an Execution Unit, a General Purpose Register File (GPR), a CPU Slave interface (CPS), and Floating Point Unit (FPU). To Program Memory Interface (PMI)
Page 57: Instruction Fetch Unit
TC1728 CPU Subsystem 2.2.2 Instruction Fetch Unit The Instruction Fetch Unit pre-fetches and aligns incoming instructions from the 64-bit wide Program Memory Interface (PMI). It contains an instruction pre-fetch buffer which may contain up to 128-bits of instructions linearly pre-fetched ahead of the current program counter.
Page 58: Execution Unit
TC1728 CPU Subsystem 2.2.3 Execution Unit The Execution Unit contains the Integer Pipeline, the Load/Store Pipeline and the Loop Pipeline. The Integer Pipeline and Load/Store Pipeline have four stages: Fetch, Decode, Execute, and Write-back. The Execute stage may extend beyond one cycle to accommodate multi-cycle operations such as load instructions.
Page 59: General Purpose Register File
TC1728 CPU Subsystem 2.2.4 General Purpose Register File The CPU has a General Purpose Register (GPR) file, divided into an Address Register File (registers A0 through A15) and a Data Register File (registers D0 through D15). The data flow for instructions issued to the Load/Store Pipeline is steered through the Address Register File.
Page 60: Cpu Implementation-Specific Features
TC1728 CPU Subsystem CPU Implementation-Specific Features This section describes the implementation-specific features of the CPU. For a complete description of all registers, refer to the TriCore Architecture Manual. 2.3.1 Context Save Areas Context Save Areas (CSA) may be placed in LDRAM.
Page 61: Interrupt System
TC1728 CPU Subsystem 2.3.3 Interrupt System An interrupt request can be generated by the on-chip peripheral units, or it can be generated by external events. Requests can be targeted to eitherthe CPU, or to the Peripheral Control Processor (PCP). The interrupt system evaluates service requests for priority and to identify whether the CPU (or PCP) should receive the request.
Page 62: Memory Integrity Error Handling
TC1728 CPU Subsystem PIE Program Memory Integrity Error (TIN 5) The PIE trap is raised whenever an uncorrectable memory integrity error is detected in an instruction fetch from a local memory. The trap is synchronous to the erroneous instruction. The trap is of Class-4 and has a TIN of 5.
Page 63 TC1728 CPU Subsystem signals are passed to the core along with their corresponding instruction half-words. Whenever an attempt is made to issue an instruction containing an uncorrectable memory integrity error a synchronous PIE trap is raised. The trap handler is then responsible for correcting the memory entry and re-starting program execution.
Page 64: Data Side Memories
TC1728 CPU Subsystem For instruction fetch requests from the TriCore CPU to ICACHE, the program tag ECC bits are read along with the data bits and an error flag is computed. A way hit is triggered only if the tag address comparison succeeds, the valid bit is set and no ECC error in the associated tag way is detected, any other result is considered a miss.
Page 65 TC1728 CPU Subsystem For write operations to LDRAM of half-word size or greater, the ECC bits are pre- calculated and written to the memory in parallel with the data bits. For byte write operations the memory transaction is transformed into a half-word read-modify-write sequence inside the DMI module.
Page 66 TC1728 CPU Subsystem uncorrectable error in the associated tag way is detected, any other result is considered a miss. In the normal case where no error is detected in either tag way then the cache line is filled/refilled as normal. In the case of a cache miss where an error is detected in...
Page 67: Tricore 1.3 Compatibility
TC1728 CPU Subsystem 2.3.5.3 TriCore 1.3 Compatibility In order to allow code written for existing TriCore 1.3 based devices to be utilised without modification, a compatibility mode is included for both the program and data side memory integrity error handling. This compatibility mode is enabled by setting the COMPAT.PIE/DIE bit(s) to one.
Page 68: Cpu Subsystem Registers
TC1728 CPU Subsystem CPU Subsystem Registers This section describes the implementation-specific features of the CPU Subsystem registers listed in Table 1. For complete descriptions of all registers refer to the TriCore Architecture Manual. Table 1 CPU Subsystem Registers Registers Purpose...
Page 69: Cpu Core Special Function Registers (Csfr)
TC1728 CPU Subsystem CPU Core Special Function Registers (CSFR) Figure 6 shows the CSFR registers of the TC1728. Program State Context Stack Information Management Management Registers Registers Registers PCXI Compatibility System Control Interrupt & Trap Register Registers Control Registers COMPAT...
Page 70 TC1728 CPU Subsystem Table 2 Core Special Function Registers (cont’d) Short Description Offset Access Mode Reset Value Name Address Read Write ICU Interrupt Control Register FE2C U, SV, SV, 32 Class 3 Reset 0000 0000 Free Context List Head FE38...
Page 71: Registers
TC1728 CPU Subsystem 2.5.1 Registers The implementation-specific Program Status Word Register (PSW) is an extension of the PSW description in the TriCore Architecture Manual. The status flags used for FPU operations overlay the status flags used for Arithmetic Logic Unit (ALU) operations.
Page 72 TC1728 CPU Subsystem Interrupt Control Register The Interrupt Control Register (ICR) is an implementation-specific CFSR. Its Arbitration Cycle Control implementation-specific details are defined in bits 24 to 26. Interrupt Control Register (F7E1 FE2C Reset Value: 0000 0000 CARBCYC PIPN CCPN...
Page 73 MMU is not available. All other bits of MMU_CON are undefined. Note: The MMU is not available in TC1728. Note: The non-shaded areas in the register description define the implementation- specific bits/bit fields. The shaded areas are defined in the TriCore Architecture Manual.
Page 74 TC1728 CPU Subsystem CPU Identification Register CPU_ID CPU Identification Register (F7E1 FE18 Reset Value: 000A C0XX MOD: 000A MOD_32B REV: xx Field Bits Type Description MOD_REV [7:0] Revision Number For version numbering. The value of the revision starts with 01...
Page 75 TC1728 CPU Subsystem Compatibility Control Register The Compatibility Control Register (COMPAT) is an implementation-specific CSFR which allows certain elements of backwards compatibility with TriCore 1.3 behaviour to be forced. The reset value of the COMPAT register ensures that backwards compatibility with TriCore 1.3 is enabled by default.
Page 76: Cpu General Purpose Registers
TC1728 CPU Subsystem CPU General Purpose Registers Figure 7 shows the General Purpose Registers (GPRs) of the TC1728. Address General Data General Purpose Registers Purpose Registers (AGPR) (DGPR) A15 (implicit address) D15 (implicit data) 64-bit Extended Data Registers A11 (return address)
Page 77 TC1728 CPU Subsystem Table 3 GPR Registers (cont’d) Short Description Offset Access Mode Reset Name Address Read Write Data Register 5 FF14 U, SV, Class 3 Reset XXXX XXXX Data Register 6 FF18 U, SV, Class 3 Reset XXXX XXXX...
Page 78 TC1728 CPU Subsystem Table 3 GPR Registers (cont’d) Short Description Offset Access Mode Reset Name Address Read Write Address Register 5 FF94 U, SV, Class 3 Reset XXXX XXXX Address Register 6 FF98 U, SV, Class 3 Reset XXXX XXXX...
Page 79: Cpu Memory Protection Registers
As shown in Figure 8, there are four Memory Protection Register Sets in the TC1728. The sets specify memory protection ranges and permissions for code and data. The PSW.PRS bit field determines which of these sets is currently in use by the CPU. The Memory Protection Registers are Core Special Function Registers, they are described in detail in the TriCore Architecture Manual.
Page 80 TC1728 CPU Subsystem Table 4 Memory Protection Registers Short Description Offset Access Mode Reset Name Address Read Write DPR0_0L Data Segment Protection C000 U, SV, Class 3 Reset Register Set 0, Range 0, 0000 0000 Lower Boundary DPR0_0U Data Segment Protection...
Page 81 TC1728 CPU Subsystem Table 4 Memory Protection Registers (cont’d) Short Description Offset Access Mode Reset Name Address Read Write DPR1_1U Data Segment Protection C40C U, SV, Class 3 Reset Register Set 1, Range 1, 0000 0000 Upper Boundary DPR1_2L Data Segment Protection...
Page 82 TC1728 CPU Subsystem Table 4 Memory Protection Registers (cont’d) Short Description Offset Access Mode Reset Name Address Read Write DPR2_3L Data Segment Protection C818 U, SV, Class 3 Reset Register Set 2, Range 3, 0000 0000 Lower Boundary DPR2_3U Data Segment Protection...
Page 83 TC1728 CPU Subsystem Table 4 Memory Protection Registers (cont’d) Short Description Offset Access Mode Reset Name Address Read Write CPR0_0U Code Segment Protection D004 U, SV, Class 3 Reset Register Set 0, Range 0, 0000 0000 Upper Boundary CPR0_1L Code Segment Protection...
Page 84 TC1728 CPU Subsystem Table 4 Memory Protection Registers (cont’d) Short Description Offset Access Mode Reset Name Address Read Write CPR3_0L Code Segment Protection DC00 U, SV, Class 3 Reset Register Set 3, Range 0, 0000 0000 Lower Boundary CPR3_0U Code Segment Protection...
Page 85: Fpu Registers
TC1728 CPU Subsystem FPU Registers A number of FPU Special Function Registers (CSFRs) have been introduced to the TriCore 1.3.1 architecture in order to fully support functional enhancements. FPU Trap Registers FPU_TRAP_CON FPU_TRAP_PC FPU_TRAP_OPC FPU_TRAP_SRCn MCA06073_2 Figure 9 TriCore 1.3.1 CSFR Registers...
Page 86: Registers
TC1728 CPU Subsystem 2.8.1 Registers FPU Identification Register FPU_ID Trapping Identification Register (F7E1 A020 Reset Value: 0054 C003 MOD: 0054 MOD_32B REV: xx Field Bits Type Description MOD_REV [7:0] Revision Number For version numbering. The value of the revision starts with 01...
Page 87: Memory Integrity Registers
TC1728 CPU Subsystem Memory Integrity Registers Memory Integrity Registers (CSFRs). Integrity Registers MIECON CCPIER CCDIER PIEAR PIETR DIEAR DIETR SMACON MCA06073-3 Figure 2-1 TriCore 1.3.1 CSFR Registers Table 2-1 Memory Integrity Registers Short Description Offset Access Mode Reset Name Address...
Page 88 TC1728 CPU Subsystem Table 2-1 Memory (cont’d) Integrity Registers Short Description Offset Access Mode Reset Name Address Read Write DIETR Data Integrity Error Trap 9024 U, SV, Class 3 Reset Register 0000 0000 SMACON SIST Mode Access Control 900C U, SV,...
Page 89: Register Descriptions
TC1728 CPU Subsystem 2.9.1 Register Descriptions Memory Integrity Error Control Register The Memory Integrity Error Control Register (MIECON) allows software to control the handling of uncorrectable memory integrity errors. MIECON Memory Integrity Error Control Register (F7E1 9044 Reset Value: 0000 0000...
Page 90 TC1728 CPU Subsystem Field Bits Type Description DTIEE Data Tag Integrity Error Enable Enables handling of uncorrectable integrity errors for the Data Tag. Uncorrectable integrity error handling disabled - all memory accesses interpreted as error free. Uncorrectable integrity error handling enabled.
Page 91 TC1728 CPU Subsystem Memory Integrity Error Control Register 2 The Memory Integrity Error Control Register 2 (MIECON2) allows software to control the handling of correctable memory integrity errors. The behaviour of MIECON2 is configured according to the tc_cfg_sec_con_en_i input to the TriCore1.3.1 core.
Page 92 TC1728 CPU Subsystem Function Although the xxIEE and xxSECE bits for a given memory type exist in different registers (MIECON and MIECON2 respectively) due to different protection requirements for these CSFR bits, the bits interact to perform the following general functions.
Page 93 TC1728 CPU Subsystem Program Integrity Error Information Registers Two architecturally visible registers (PIETR, PIEAR) allow software to localise the source of the last detected uncorrectable program memory integrity error. These registers are updated when an uncorrectable program integrity error condition is detected and the PIETR.IED bit is zero.
Page 94 TC1728 CPU Subsystem Program Integrity Error Trap Register (PIETR) PIETR Program Integrity Error Trap Register (F7E1 9214 Reset Value: 0000 0000 BUS_ID IE_B IE_S IE_C IE_T IED Field Bits Type Description Integrity Error Detected Read Operation: No program integrity error condition occurred.
Page 95 TC1728 CPU Subsystem Program Integrity Error Address Register This register contains the physical address accessed by the operation that encountered a uncorrectable program memory integrity error. This register is only updated if PIETR.IED is zero. PIEAR Program Integrity Error Address Register...
Page 96 TC1728 CPU Subsystem Data Integrity Error Information Registers Two architecturally visible registers (DIETR, DIEAR) allow software to localise the source of the last detected uncorrectable data memory integrity error. These registers are updated when an uncorrectable data integrity error condition is detected and the DIETR.IED bit is zero.
Page 97 TC1728 CPU Subsystem Data Integrity Error Trap Register (DIETR) DIETR Data Integrity Error Trap Register (F7E1 9024 Reset Value: 0000 0000 BUS_ID IE_B IE_S IE_C IE_T IED Field Bits Type Description Integrity Error Detected Read Operation: No data integrity error condition occurred.
Page 98 TC1728 CPU Subsystem Field Bits Type Description [31:10] Reserved Read as 0; should be written with 0. User’s Manual 2-45 V1.0, 2011-12 CPU, V3.03...
Page 99 TC1728 CPU Subsystem Data Integrity Error Address Register This register contains the physical address accessed by the operation that encountered a uncorrectable data memory integrity error. This register is only updated if DIETR.IED is zero. DIEAR Data Integrity Error Address Register...
Page 100 TC1728 CPU Subsystem SIST (Software In-System) Test Support The TriCore 1.3.1 core protects against memory integrity errors by ECC protection of the on-core memories. This has the side-effect of requiring memory blocks wider than the normal data access path to the memory. The additional ECC storage bits are not easily accessible via the existing data paths, causing problems where SIST based testing of the memories is required.
Page 101 TC1728 CPU Subsystem Field Bits Type Description [1:0] Instruction Cache Memory SIST Mode Access control Normal Operation, No Mapping. Instruction cache memory configured as program SPR. [3:2] Program Tag Memory SIST Mode Access Control Normal Operation, No Mapping. Data Array Mapping, no error detection/correction.
Page 102 TC1728 CPU Subsystem Field Bits Type Description [13:12] Data Scratch Memory SIST Mode Access Control Normal Operation, No Mapping, Performance Optimised. Data Array Mapping, no error detection/correction. Check Array Mapping, no error detection/correction. Data Array Mapping, error detection/correction enabled. IODT...
Page 103 TC1728 CPU Subsystem Control Fields The control fields within the SMACON register allow individual control of the local memories. Each memory may be mapped to operate in a number of different modes. Normal operation, No Mapping No mapping of the memories is performed and normal operation is possible. Embedded memories not usually directly addressable are not accessible in the system address map.
Page 104: Cpu Slave Interface (Cps) Registers
TC1728 CPU Subsystem 2.10 CPU Slave Interface (CPS) Registers The CPU Slave Interface (CPS) of the TriCore CPU directly accesses the interrupt service request registers in the CPU from the System Peripheral Bus. The CPS registers are described in detail in the TriCore Architecture Manual.
Page 105: Register Descriptions
TC1728 CPU Subsystem 2.10.1 Register Descriptions This registers have a specific implementation detail, the Type of Service Control (TOS) bit/bit field. CPU Service Request Control Register CPU_SRCn (n = 0-3) CPU Service Request Control Register n (F7E0 FFFC -n*4) Reset Value: 0000 0000...
Page 106 TC1728 CPU Subsystem CPS Module Identification Register CPS_ID CPS Module Identification Register (F7E0 FF08 Reset Value: 0015 C0XX MOD: 0015 MOD_32B REV: xx Field Bits Type Description MOD_REV [7:0] Revision Number For version numbering. The value of the revision starts with 01...
Page 107 TC1728 CPU Subsystem CPU Software Breakpoint Service Request Control Register CPU_SBSRC CPU Software Breakpoint Service Request Control Register Reset Value: 0000 0000 (F7E0 FFBC SRR SRE SRPN Field Bits Type Description Type of Service Control Service Provider = CPU Reserved Reserved Read as 0;...
Page 108: Core Debug Registers
TC1728 CPU Subsystem 2.11 Core Debug Registers The Core Debug registers are available for debug purposes. For a complete description of all registers, refer to the TriCore Architecture Manual. Performance Core Debug Counter Registers Registers CCTRL DBGSR CCNT EXEVT ICNT...
Page 109 TC1728 CPU Subsystem Table 8 Core Debug Registers (cont’d) Short Description Offset Access Mode Reset Name Address Read Write EXEVT External Break Input Event FD08 U, SV, SV, 32 Class 1 Reset Register 0000 0000 CREVT Core SFR Access Break...
Page 110: Implementation Specific Reset Values
TC1728 CPU Subsystem 2.12 Implementation Specific Reset Values This section summarizes the implementation specific reset values of the CPU registers not defined in this chapter. Table 9 Implementation Specific Reset Values Register Address Reset Value PCXI F7E1 FE00 0000 0000...
Page 111: Cpu Instruction Timing
TC1728 CPU Subsystem 2.13 CPU Instruction Timing This section gives information on CPU instruction timing by execution unit. The Integer Pipeline and Load/Store Pipeline are always present, and the Floating Point Unit (FPU) is optional. The Load/Store unit implements the optional TLB instructions.
Page 112: Integer-Pipeline Instructions
TC1728 CPU Subsystem 2.13.1 Integer-Pipeline Instructions These are the Integer-Pipeline instruction timings for each instruction. 2.13.1.1 Simple Arithmetic Instruction Timings Each instruction is single issued. Table 10 Simple Arithmetic Instruction Timing Instruction Result Repeat Instruction Result Repeat Latency Rate Latency...
Page 113 TC1728 CPU Subsystem Table 10 Simple Arithmetic Instruction Timing (cont’d) Instruction Result Repeat Instruction Result Repeat Latency Rate Latency Rate CSUB SUBS.H CSUBN SUBS.HU SUBS.U MAX.B SUBX MAX.BU Compare Instructions LT.B EQ.B LT.BU EQ.H LT.H EQ.W LT.HU EQANY.B LT.U EQANY.H LT.W...
Page 114 TC1728 CPU Subsystem Table 10 Simple Arithmetic Instruction Timing (cont’d) Instruction Result Repeat Instruction Result Repeat Latency Rate Latency Rate AND.GE.U OR.NE AND.LT OR.NOR.T AND.LT.U OR.OR.T AND.NE OR.T AND.NOR.T AND.OR.T ORN.T AND.T XNOR ANDN XNOR.T ANDN.T NAND XOR.EQ NAND.T XOR.GE XOR.GE.U...
Page 115 TC1728 CPU Subsystem Table 10 Simple Arithmetic Instruction Timing (cont’d) Instruction Result Repeat Instruction Result Repeat Latency Rate Latency Rate SH.NAND.T Coprocessor 0 Instructions BMERGE DVSTEP BSPLIT DVSTEP.U DVADJ IXMAX DVINIT IXMAX.U DVINIT.U IXMIN DVINIT.B IXMIN.U DVINIT.H PACK DVINIT.BU PARITY DVINIT.HU...
Page 116: Multiply Instruction Timings
TC1728 CPU Subsystem 2.13.1.2 Multiply Instruction Timings Each instruction is single issued. Table 11 Multiply Instruction Timing Instruction Result Repeat Instruction Result Repeat Latency Rate Latency Rate MUL.Q MUL.U MULM.H MULS MULR.H MULS.U MULR.Q MUL.H User’s Manual 2-63 V1.0, 2011-12...
Page 117: Multiply Accumulate (Mac) Instruction Timing
TC1728 CPU Subsystem 2.13.1.3 Multiply Accumulate (MAC) Instruction Timing Each instruction is single issued. Table 12 Multiply Accumulate Instruction Timing Instruction Result Repeat Instruction Result Repeat Latency Rate Latency Rate MADD MSUB MADD.U MSUB.U MADDS MSUBS MADDS.U MSUBS.U MADD.H MSUB.H MADD.Q...
Page 118: Control Flow Instruction Timing
TC1728 CPU Subsystem 2.13.1.4 Control Flow Instruction Timing Note all Integer Pipeline Control flow instructions are conditional. • Each instruction is single issued. • All target locations yield a full instruction in one access (i.e. not 16-bits of a 32-bit instruction).
Page 119: Load-Store Pipeline Instructions
TC1728 CPU Subsystem 2.13.2 Load-Store Pipeline Instructions This section summarizes the Load-Store Pipeline instructions. 2.13.2.1 Address Arithmetic Timing Each instruction is single issued. Table 14 Address Arithmetic Instruction Timing Instruction Result Repeat Instruction Result Repeat Latency Rate Latency Rate Load Store Arithmetic Instructions ADD.A...
Page 120: Control Flow Instruction Timing
TC1728 CPU Subsystem 2.13.2.2 Control Flow Instruction Timing This section summarizes the timing of Control Flow instructions. Each instruction is single issued. • All targets yield a full instruction in one access (not 16-bits of a 32-bit instruction). • All code fetches take a single cycle. Timing is best case; no cache misses for context operations, no pending stores.
Page 121: Load Instruction Timing
TC1728 CPU Subsystem For JLI, JEQ.A, JNE.A JNZ.A, JZ.A Instructions: Flow Latency Repeat Rate Correctly predicted, not taken Correctly predicted, taken Wrongly predicted 2.13.2.3 Load Instruction Timing Load instructions can produce two results if they use the pre-increment, post-increment, circular or bit-reverse addressing modes. Hence, in those cases there are two latencies that must be specified, the result latency for the value loaded from memory and the address latency for using the updated address register result.
Page 122: Store Instruction Timing
TC1728 CPU Subsystem 2.13.2.4 Store Instruction Timing Cache and Store instructions similar to Load instructions will have a result for the pre- increment, post-increment, circular or bit-reverse addressing modes, but do not produce a ‘memory’ result. • Each instruction is single issued.
Page 123: Floating Point Pipeline Timing
TC1728 CPU Subsystem 2.13.3 Floating Point Pipeline Timing These instructions are only valid if the optional Floating Point Unit is implemented. Each instruction is single issued. Table 18 Floating Point Instruction Timing Instruction Result Repeat Instruction Result Repeat Latency Rate...
Page 124: Program Memory Interface (Pmi)
TC1728 CPU Subsystem 2.14 Program Memory Interface (PMI) Figure 12 shows the block diagram of the Program Memory Interface (PMI) of the TC1728. Program Memory Interface (PMI) To/From PMEM Data Switch ICACHE & Data Alignment & Interface Control SPRAM Control...
Page 125: Lmb Access Priorities
5. PMI 6. DMA Low 2.14.3 Scratchpad RAM The TC1728 contains up to 24 Kbyte of scratchpad RAM. Scratchpad RAM provides a fast, deterministic program fetch access from the CPU for use by performance critical code sequences. • CPU program fetch accesses to scratchpad RAM are never cached in the instruction cache and are always directly targeted to the scratchpad RAM.
Page 126: Instruction Cache
The scratchpad RAM may also be accessed from the LMB Slave interface by another bus master, such as the Data Memory Interface (DMI). The scratchpad RAM may be both read and written from the LMB. In the TC1728, the PMI LMB Slave interface supports all LMB transaction types.
Page 127: Program Line Buffer
TC1728 CPU Subsystem Instruction Cache Bypass The Instruction Cache may be bypassed, under control of PMI_CON0.PCBYP, to provide a direct instruction fetch path for the CPU Fetch Unit. The default value of PMI_CON0.PCBYP is such that the ICACHE is bypassed after reset. ICACHE bypass should be disabled during initialization to enable the ICACHE.
Page 128: Pmi Registers
TC1728 CPU Subsystem 2.14.6 PMI Registers Three control registers are implemented in the Program Memory Interface. These registers and their bits are described in this section. PMI Control Registers PMI_CON0 PMI_CON1 PMI_CON2 PMI_STR MCA06079-1 Figure 13 PMI Registers Table 19...
Page 129: Pmi Register Descriptions
TC1728 CPU Subsystem 2.14.6.1 PMI Register Descriptions PMI Control Register 0 PMI_CON0 PMI Control Register 0 (F87F FD10 Reset Value: 0000 0002 Field Bits Type Description PCBYP Instruction Cache Bypass Cache enabled Cache bypassed (disabled) [31:2], Reserved Read as 0; should be written with 0.
Page 130 TC1728 CPU Subsystem PMI Control Register 1 PMI_CON1 PMI Control Register 1 (F87F FD14 Reset Value: 0000 0000 Field Bits Type Description PCINV Instruction Cache Invalidate Write Operation: No effect. Normal instruction cache operation. Initiate invalidation of entire instruction cache.
Page 131 TC1728 CPU Subsystem PMI Control Register 2 The PMI_CON2 register may only be written in supervisor mode and is endinit protected. In addition write accesses to PMI_CON2 are also dependent on the status of Flash read protection. Whenever Flash read protection is inactive PMI_CON2 may be written as often as required (bearing in mind operational constraints for changing SRAM and cache sizes).
Page 132 TC1728 CPU Subsystem Field Bits Type Description PC_SZ_CFG [19:16] rwh Instruction Cache Size Configuration Configuration of the Instruction Cache Size. Any program memory not utilised as instruction cache is configured as SPRAM. After reset this field is set to zero. This field may subsequently be written to select...
Page 133 TC1728 CPU Subsystem Program Memory Interface Synchronous Trap Register (PMI_STR) PMI_STR PMI Synchronous Trap Register (F87F FD20 Reset Value: 0000 0000 Field Bits Type Description FRESTF Fetch Range Error Synchronous Trap Flag FBESTF Fetch Bus Error Synchronous Trap Flag FPESTF...
Page 134 TC1728 CPU Subsystem PMI Identification Register PMI_ID PMI Identification Register (F87F FD08 Reset Value: 000B C0XX MOD: 000B MOD_32B REV: xx Field Bits Type Description MOD_REV [7:0] Revision Number For version numbering. The value of the revision starts with 01...
Page 135: Data Memory Interface (Dmi)
TC1728 CPU Subsystem 2.15 Data Memory Interface (DMI) This figure shows the block diagram of the Data Memory Interface (DMI) of the TC1728. Data Memory Interface (DMI) Data Switch DMEM & Data Alignment DCache & Interface Control LDRAM Control Registers...
Page 136: Lmb Access Priorities
2.15.4 Data Cache The TC1728 contains up to 4 KByte of Data Cache (DCache). The DCache is a two-way set-associative cache with a Least-Recently-Used (LRU) replacement algorithm, and is organised as 256 cache lines, with 128-bits per line. Associated with each DCache line is a single valid bit which pertains to the entire line.
Page 137: Data Line Buffer
The TC1728 data cache is of the writeback type. When the CPU writes to a cacheable location the data is merged with the corresponding cache line and not written to main memory immediately.
Page 138: Dmi Trap Generation
TC1728 CPU Subsystem A single valid bit is associated with the DLB, denoting that the DLB contents are valid. As such all accesses updating the DLB, whether data cache is configured or not, are implemented as LMB Burst Transfer 2 (BTR2) transactions, with the critical double-word of the DLB line being fetched first size.
Page 139 TC1728 CPU Subsystem Cache Writeback Error Cache writeback errors are detected when a data cache or DLB writeback sequence, initiated by a CPU load-store access generating a cache miss, encounters a bus error on the LMB. Note that unlike other error types, the address causing a cache writeback error is not related to the address of the CPU load-store access which caused the writeback.
Page 140: Dmi Registers
TC1728 CPU Subsystem 2.15.7 DMI Registers Two Control Registers, two Trap Flag registers, and four Error Detection registers are implemented in the DMI. These registers and their bits are described in this section. Control Trap Flag Error Detection Registers Registers...
Page 141 TC1728 CPU Subsystem read-only register, will lead to a bus error if the access was from the LMB Bus, or to a trap, flagged in DMI_STR/DMI_ATR register in case of a CPU load/store access. User’s Manual 2-88 V1.0, 2011-12 CPU, V3.03...
Page 142: Dmi Register Descriptions
TC1728 CPU Subsystem 2.15.7.1 DMI Register Descriptions DMI Control Register The DMI control register indicates the DMI data memory size and data cache availability. DMI_CON DMI Control Register (F87F FC10 Reset Value: 0780 0782 DMEM_SZ_CFG DC_SZ_CFG DMEM_SZ_AV DC_SZ_AV Field Bits...
Page 143 TC1728 CPU Subsystem Field Bits Type Description DMEM_SZ_CF [31:20] rwh Data Memory Size Configuration Configuration of the Data Memory (DMEM) size. After reset this field is set to equal the maximum DMEM size available, DMEM_SZ_AV. This field may subsequently be written to force a smaller DMEM size to be visible to software .
Page 144 TC1728 CPU Subsystem DMI Synchronous Trap Flag Register The DMI Synchronous Trap Flag Register, DMI_STR, holds the flags that identify the root cause of a Data-access Synchronous Bus Error (DSE). Reading DMI_STR in supervisor mode returns the register contents and then clears its contents. Reading DMI_STR in user mode returns the contents of the register but does not clear its contents.
Page 145 TC1728 CPU Subsystem DMI Asynchronous Trap Flag Register The DMI Asynchronous Trap Flag Register, DMI_ATR, holds the flags that inform about the root cause of a Data Access Asynchronous Bus Error (ASE). Reading DMI_ATR in supervisor mode returns the register contents and then clears its contents. Reading DMI_ATR in user mode returns the contents of the register but does not clear its contents.
Page 146 TC1728 CPU Subsystem DMI Identification Register DMI_ID DMI Identification Register (F87F FC08 Reset Value: 0008 C0XX MOD: 0008 MOD_32B REV: xx Field Bits Type Description MOD_REV [7:0] Revision Number For version numbering. The value of the revision starts with 01...
Page 147 CPU Subsystem LMB Error Injection Control Registers The LMB bus system of the TC1728 processor is protected against transmission errors caused by transient events. All signal groups - address group signals (address, bus opcode, etc.), data signals and response group signals are ECC protected, allowing the detection and signalling of single- or double-bit errors in the transmission protocol.
Page 148 TC1728 CPU Subsystem Address Error Detection Control Register The ADEDCTL register enables the injection of errors on the ECC bits associated with the LMB address signal group and / or the complemented LMB abort signal, for transactions generated by the DMI LMB master interface. It may be used to check the...
Page 149 TC1728 CPU Subsystem Field Bits Type Description IENABLE Idle Enable Enables corruption of address signal group ECC bits for the next non-excluded idle cycle generated by the DMI LMB master when acting as LMB default master. Not enabled Enabled Cleared by hardware after a non-excluded idle cycle driven by the DMI has completed.
Page 150 TC1728 CPU Subsystem Write Data Error Detection Control Register The WREDCTL register enables the injection of errors on the ECC bits associated with the LMB data signals, for LMB write transactions generated by the DMI LMB master interface. It may be used to check the write data error detection functionality of any LMB...
Page 151 TC1728 CPU Subsystem This register is ENDINIT protected. User’s Manual 2-98 V1.0, 2011-12 CPU, V3.03...
Page 152 TC1728 CPU Subsystem Read Data Error Detection Control Register The RDEDCTL register enables the injection of errors on the ECC bits associated with the LMB data signals, for LMB read transactions targetting the DMI LMB slave interface. It may be used to check the read data error detection functionality of any LMB master...
Page 153 TC1728 CPU Subsystem This register is ENDINIT protected User’s Manual 2-100 V1.0, 2011-12 CPU, V3.03...
Page 154 TC1728 CPU Subsystem Response Error Detection Control Register The REEDCTL register enables the injection of errors on the ECC bits associated with the LMB response signal group, for LMB transactions targetting the DMI LMB slave interface. It may be used to check the response error detection functionality of any LMB...
Page 155 TC1728 CPU Subsystem This register is ENDINIT protected. User’s Manual 2-102 V1.0, 2011-12 CPU, V3.03...
Page 156: System Control Unit (Scu)
TC1728 System Control Unit (SCU) System Control Unit (SCU) The System Control Unit (SCU) of the TC1728 handles all system control tasks beside the debug related tasks which are controlled by the OCDS/Cerberus. The SCU contains the following functional sub-blocks: •...
Page 157: Clock System Overview
TC1728 System Control Unit (SCU) Clock System Overview This section describes the TC1728 clock system. Topics covered include clock generation and the operation of clock circuitry. The TC1728 clock system provides the following functions: • Acquires and buffers incoming clock signals to create a master clock frequency •...
Page 158 L MB MSC0 MC D S EXTCLK1 FL EX CCU6061 EXTCLK0 ADC0 MCDS ADC1 MLI 0 ERAY Domain FADC FL EX ERAY GPT120 GPT121 Toplevel _clock_172 X . Figure 3-1 TC1728 Clocking System User’s Manual V1.0, 2011-12 32-bit Platform SCU, V1.0...
Page 159: Clock Generation Unit
System Control Unit (SCU) 3.1.1 Clock Generation Unit The Clock Generation Unit (CGU) allows a very flexible clock generation for the TC1728. During user program execution the frequency can be programmed for an optimal ratio between performance and power consumption.
Page 160: Oscillator Circuit (Osc)
XTAL1 Signal XTAL2 ext_clk_inl_mode Figure 3-3 TC1728 Direct Clock Input External Crystal / Ceramic Resonator Mode Figure 3-4 shows the recommended external circuitries for both operating modes, External Crystal / Ceramic Resonator Mode with and without external components. User’s Manual V1.0, 2011-12...
Page 161 TC1728 System Control Unit (SCU) XTAL1 XTAL1 XTAL2 XTAL2 without external Components with external Components ext_crystal _ mode Figure 3-4 External Circuitry for Crystal / Ceramic Resonator operation Oscillator Module XTAL1 XTAL2 adjustable adjustable Load Caps Load Caps external Component 6.5pF...
Page 162: Phase-Locked Loop (Pll) Module
TC1728 System Control Unit (SCU) circuitry must be used, connected to both pins, XTAL1 and XTAL2. Additionally are necessary, two load capacitances , and depending on the crystal / ceramic resonator type, a series resistor to limit the current. A test resistor...
Page 163 TC1728 System Control Unit (SCU) PLL Functional Description The PLL consists of a Voltage Controlled Oscillator (VCO) with a feedback path. A divider in the feedback path (N-Divider) divides the VCO frequency down. The resulting frequency is then compared with the externally provided and divided frequency (P- Divider).
Page 164 TC1728 System Control Unit (SCU) The output frequency is given by (3.1) ⋅ -------------- - f f PLL ⋅ P K2 Prescaler Mode In Prescaler Mode the reference frequency is only divided down by a factor K1. The output frequency is given by (3.2)
Page 165 TC1728 System Control Unit (SCU) Note: f has to be within the range of 2 MHz to 3 MHz and should be as close as OSCREF possible to 2.5 MHz. Before configuring the OSC_WDT function all the trap options should be disabled in order to avoid unintended traps.
Page 166 TC1728 System Control Unit (SCU) • PLLCON0.VCOBYP = 0 • PLLCON0.SETFINDIS = 1 The Freerunning Mode is entered when • PLLSTAT.FINDIS = 1 • • PLLSTAT.VCOBYST = 0 Operation on the Freerunning Mode does not require an input clock frequency of The Freerunning Mode is automatically entered on a PLL VCO Loss-of-Lock event if bit PLLCON0.OSCDISCDIS is cleared.
Page 167 TC1728 System Control Unit (SCU) The output frequency is given by: (3.6) f OSC ------------- - f PLL The Prescaler Mode is selected by the following settings • PLLCON0.VCOBYP = 1 The Prescaler Mode is entered when the following requirements are all together valid: •...
Page 168 TC1728 System Control Unit (SCU) PLLSTAT . FINDIS Divider Divider Lock Detect. Osc. Divider PLLCON 0. VCOBYP PLL Block PLL_Normal_Mode. vsd Figure 3-9 PLL Normal Mode Diagram The output frequency is given by: (3.7) ⋅ -------------- - f f PLL ⋅...
Page 169 TC1728 System Control Unit (SCU) of the K2-divider has no impact on the VCO Lock status but still changes the PLL output frequency. Note: When configuring the PLL for the first time after a system reset it is recommended to disconnect the input clock fOSC before configuring P, N, and K2 and connect fOSC before checking for the lock status.
Page 170: Eray Phase-Locked Loop (Pll_Eray) Module
TC1728 System Control Unit (SCU) frequency changes. Between the update of two K2-Divider values 6 cycles of should be waited. PLL VCO Lock Detection The PLL has a lock detection that supervises the VCO part of the PLL in order to differentiate between stable and instable VCO circuit behavior.
Page 171 TC1728 System Control Unit (SCU) Features • VCO lock detection • 6-bit feedback divider N: (multiply by NDIV+1) • 5-bit output divider K1 or K2: (divide by either by K1DIV+1 or K2DIV+1) • Different operating modes – Prescaler Mode – Freerunning Mode –...
Page 172 TC1728 System Control Unit (SCU) PLL_ERAY Block K1- Divider PLL_ERAY K2- Divider Lock- Detection Divider PLLERAY _block Figure 3-10 PLL_ERAY Block Diagram Clock Source Control The PLL_ERAY clock is generated from in one of three software selectable PLL_ERAY modes: •...
Page 173 TC1728 System Control Unit (SCU) In Prescaler Mode the reference frequency is only divided down by a factor K1. The output frequency is given by (3.9) f OSC ------------- - f PLL Freerunning Mode In Freerunning Mode the base frequency output of the Voltage Controlled Oscillator (VCO) is only divided down by a factor K2.
Page 174 TC1728 System Control Unit (SCU) The output frequency is given by (3.11) f VCObase -------------------------- - f PLL The Freerunning Mode is selected by the following settings • PLLERAYCON0.VCOBYP = 0 • PLLERAYCON0.SETFINDIS = 1 The Freerunning Mode is entered when •...
Page 175 TC1728 System Control Unit (SCU) Divider PLL_ERAY PLLERAY CON0. VCOBY P PLL_ERAY Block PLLERAY _N_Prescaler _Mode. vsd Figure 3-12 PLL_ERAY Prescaler Mode Diagram The output frequency is given by: (3.12) f OSC ------------- - f PLL The Prescaler Mode is selected by the following settings •...
Page 176 TC1728 System Control Unit (SCU) The Prescaler Mode is requested from the Freerunning or Normal Mode by setting bit PLLERAYCON.VCOBYP. The Prescaler Mode is entered when the status bit PLLERAYSTAT.VCOBYST is set. Before the Prescaler Mode is requested the K1-...
Page 177 TC1728 System Control Unit (SCU) • PLLERAYSTAT.VCOBYST = 0 • PLLERAYSTAT.VCOLOCK = 1 • OSCCON.PLLLV = 1 • OSCCON.PLLHV = 1 Operation on the Normal Mode does require an input clock frequency of . Therefore it is recommended to check and monitor if an input frequency is available at all by checking OSCCON.PLLLV.
Page 178: Clock Control Unit
TC1728 System Control Unit (SCU) Depending on the selected divider value of the K2-Divider the duty cycle of the clock is selected. This can have an impact for the operation with an external communication interface. The duty cycles values for the different K2-divider values are defined in the Data Sheet.
Page 179: External Clock Output
CCU_block . Figure 3-14 Clock Control Unit The clocking system of the TC1728 consists of the Clock Control Unit (CCU) and the Clock Generation Unit. There is also a fix reference clock REFCLK1 for the MCDS block which divides the master clock by 24.
Page 180 TC1728 System Control Unit (SCU) Additionally a connection to the GPTA module is implemented to support the start-up control of an external crystal for the device clock generation. The first time before the master clock is generated based on a external crystal 1000 cycles of the crystal clock should be waited before the clock control system is changed to External Crystal Mode.
Page 181 TC1728 System Control Unit (SCU) clock is thereafter divider additionally by a factor of two to guarantee a 50% duty cycle and outputs the clock, . The fractional divider is controlled by the FDR register. Figure 3-16 shows the fractional divider block diagram.
Page 182 TC1728 System Control Unit (SCU) Normal Divider Mode In Normal Divider Mode (FDR.DM = 01 ), the fractional divider behaves as a reload counter (addition of +1) that generates an output clock pulse on the transition from 3FF to 000 .
Page 183 TC1728 System Control Unit (SCU) EXTCON.SEL1 EXTCON.DIV1 Reserved Reserved Reserved Reserved EXTCON.EN1 Reserved Reserved P4.2 Reserved Reserved Reserved EXTCON.NSEL Reserved Reserved Reserved Reserved Reserved extclk . Figure 3-17 EXTCLK1 Generation Clock is generated via a counter, so the output frequency can be selected in small steps.
Page 184: Cgu Registers
TC1728 System Control Unit (SCU) 3.1.1.7 CGU Registers System Oscillator Register This register controls the settings of OSC. OSCCON OSC Control Register (010 Reset Value: 0000 001C OSCVAL MODE GAINSEL Field Bits Type Description PLLLV Oscillator for PLL Valid Low Status Bit This bit indicates if the frequency output of OSC is usable for the VCO part of the PLL.
Page 185 TC1728 System Control Unit (SCU) Field Bits Type Description MODE [6:5] Oscillator Mode This bit field defines which mode can be used and if the oscillator entered the Power-Saving Mode or not. External Crystal Mode and External Input Clock Mode. The oscillator Power-Saving Mode is not entered.
Page 186 TC1728 System Control Unit (SCU) Field Bits Type Description OSCVAL [20:16] rw OSC Frequency Value This bit field defines the divider value that generates the reference clock that is supervised by the oscillator watchdog. is divided by OSCVAL + 1...
Page 187 TC1728 System Control Unit (SCU) Field Bits Type Description VCOLOCK PLL VCO Lock Status The frequency difference of greater than allowed. The VCO part of the PLL can not lock on a target frequency. The frequency difference of small enough to enable a stable VCO operation.
Page 188 TC1728 System Control Unit (SCU) Field Bits Type Description K2RDY K2 Divider Ready Status This bit indicates if the K2-divider operates on the configured value or not. this is of interest if the values is changed. K2-Divider is not ready to operate with the new...
Page 189 TC1728 System Control Unit (SCU) Field Bits Type Description SETFINDIS Set Status Bit PLLSTAT.FINDIS Bit PLLSTAT.FINDIS is left unchanged Bit PLLSTAT.FINDIS is set. The input clock from the oscillator is disconnected from the VCO part. CLRFINDIS Clear Status Bit PLLSTAT.FINDIS Bit PLLSTAT.FINDIS is left unchanged...
Page 190 TC1728 System Control Unit (SCU) PLLCON1 PLL Configuration 1 Register (01C Reset Value: 0002 000F K1DIV K2DIV Field Bits Type Description K2DIV [6:0] K2-Divider Value The value the K2-Divider operates is K2DIV+1. K1DIV [22:16] rw K1-Divider Value The value the K1-Divider operates is K1DIV+1.
Page 191 TC1728 System Control Unit (SCU) Field Bits Type Description VCOBYST VCO Bypass Status Freerunning / Normal Mode is entered Prescaler Mode is entered PWDSTAT PLL_ERAY Power-saving Mode Status PLL_ERAY Power-saving Mode was not entered PLL_ERAY Power-saving Mode was entered VCOLOCK...
Page 192 TC1728 System Control Unit (SCU) Field Bits Type Description K1RDY K1 Divider Ready Status This bit indicates if the K1-divider operates on the configured value or not. this is of interest if the values is changed. K1-Divider is not ready to operate with the new...
Page 193 TC1728 System Control Unit (SCU) Field Bits Type Description VCOPWD VCO Power Saving Mode Normal behavior The VCO is put into a Power Saving Mode and can no longer be used. SETFINDIS Set Status Bit PLLERAYSTAT.FINDIS Bit PLLERAYSTAT.FINDIS is left unchanged Bit PLLERAYSTAT.FINDIS is set.
Page 194 TC1728 System Control Unit (SCU) PLLERAYCON1 PLL_ERAY Configuration 1 Register (02C Reset Value: 000F 000F K1DIV K2DIV Field Bits Type Description K2DIV [6:0] K2-Divider Value The value the K2-Divider operates is K2DIV+1. K1DIV [22:16] rw K1-Divider Value The value the K1-Divider operates is K1DIV+1.
Page 195 TC1728 System Control Unit (SCU) Field Bits Type Function FPIDIV [3:0] FPI-Bus Divider Reload Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 LMBDIV [11:8] LMB-Bus Divider Reload Value 0000 0001 0010...
Page 196 TC1728 System Control Unit (SCU) Field Bits Type Function Lock Status This bit indicates if the register can be updated with a new value or if the register is locked and a write action from the bus side has no effect.
Page 197 TC1728 System Control Unit (SCU) Field Bits Type Function MCDSDIV [3:0] MCDS Divider Reload Value 0000 MCDS 0001 MCDS 0010 MCDS 0011 MCDS 0100 MCDS 0101 MCDS 0110 MCDS 0111 MCDS 1000 MCDS 1001 MCDS 1010 MCDS 1011 MCDS 1100...
Page 198 TC1728 System Control Unit (SCU) Field Bits Type Function Lock Status This bit indicates if the register can be updated with a new value or if the register is locked and a write action from the bus side has no effect.
Page 199 TC1728 System Control Unit (SCU) Field Bits Type Function ERAYDIV [3:0] ERAY-Bus Divider Reload Value 0000 ERAY PLL_ERAY 0001 ERAY PLL_ERAY 0010 ERAY PLL_ERAY 0011 ERAY PLL_ERAY 0100 ERAY PLL_ERAY 0101 ERAY PLL_ERAY 0110 ERAY PLL_ERAY 0111 ERAY PLL_ERAY 1000...
Page 200 TC1728 System Control Unit (SCU) EXTCON External Clock Control Register (03C Reset Value: 0000 0000 DIV1 SEL1 AINS SEL0 Field Bits Type Description External Clock Enable for EXTCLK0 No external clock is provided The configured external clock is provided SEL0...
Page 201 TC1728 System Control Unit (SCU) Field Bits Type Description SEL1 [21:18] rw External Clock Select for EXTCLK1 This bit field defines the clock source that is selected as output for pin EXTCLK1. 0000 is selected for the external clock 0001...
Page 202 TC1728 System Control Unit (SCU) Field Bits Type Description [15:14] Divider Mode This bit fields determines the functionality of the fractional divider block. Fractional divider is switched off; no output clock is generated. The Reset External Divider signal is 1. RESULT is not updated (default after System Reset).
Page 203: Module Clock Generation
TC1728 System Control Unit (SCU) 3.1.2 Module Clock Generation The TC1728 on-chip modules have two registers for clock control: • Clock Control Register CLC • Fractional Divider Register FDR The following sections describes the general functionality of CLC and FDR. The module- specific implementation details are described in the corresponding module chapters.
Page 204: Clock Control Register Clc
TC1728 System Control Unit (SCU) 3.1.2.1 Clock Control Register CLC All CLC registers have basically the same bit and bit field layout. However, not all CLC register functions are implemented for each peripheral module. Table 3-1 defines in detail which bits and bit fields of the CLC registers are implemented for each clock control register.
Page 205 When an application is suspended, normal operation of the application’s program is halted, and the TC1728 begins (or resumes) executing a special debug monitor program. If bit SPEN is set, the operation of the peripheral module is stopped when the Suspend Mode request is generated.
Page 206 SPEN bit. Module Clock Divider Control Peripheral modules of the TC1728 can have a RMC control bit field in their CLC registers. This Run Mode Clock control bit field makes it possible to slow down the CLC clock via a programmable clock divider circuit.
Page 207 Module Clock Register Implementations Table 3-1 shows which of the CLC register bits/bit fields are implemented for each peripheral module in the TC1728 and which modules are equipped with a fractional divider. Table 3-1 Clock Generation Implementation of the TC1728 Peripheral Modules...
Page 208 TC1728 System Control Unit (SCU) Table 3-1 Clock Generation Implementation of the TC1728 Peripheral Modules Module DISR DISS SPEN EDIS SBWE FSOE Fract. Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Divider – – – –...
Page 209 TC1728 System Control Unit (SCU) STEP Reload Reload Reload RESULT C L C MCT05605_m Figure 3-18 Normal Divider Mode Fractional divider Mode When the Fractional Divider Mode is selected (MOD_FDR.DM = 10 ), the module clock is derived from the bus clock by division of a fraction of n/1024 for any value of n from 0 to 1023.
Page 210 TC1728 System Control Unit (SCU) and (Suspend Mode Acknowledge or bit SM) must remain set both to maintain the Suspend Mode. The Kernel Disable Request becomes always active when the Module Disable Request signal is activated, independently of the Suspend Mode settings in the fractional divider.
Page 211 TC1728 System Control Unit (SCU) Table 3-2 Fractional Divider Function Table Mode Result Operation of Fractional Divider Normal Mode – unchanged inactive switched off continuously active Normal Divider updated Mode Fractional Divider Mode unchanged inactive switched off Suspend unchanged inactive...
Page 212 TC1728 System Control Unit (SCU) Table 3-3 FDR Register Implementations FDR Register Suspend Mode Acknowledge Operation ENHW CAN_FDR Acknowledge depends on module state – GPTA0_FDR Always immediately acknowledged; from independently from module states MultiCAN MLI0_FDR Acknowledge depends on module state –...
Page 213 TC1728 System Control Unit (SCU) Module CLC Register MOD_CLC Clock Control Register Reset Value: Module-specific Field Bits Type Description DISR Module Disable Request Bit Used for enable/disable control of the module. Module disable is not requested Module disable is requested...
Page 214 TC1728 System Control Unit (SCU) Field Bits Type Description SBWE Module Suspend Bit Write Enable for OCDS Determines whether SPEN and FSOE are write- protected. Bits SPEN and FSOE are write-protected Bits SPEN and FSOE are overwritten by respective value of SPEN or FSOE Reading this bit returns always 0.
Page 215 TC1728 System Control Unit (SCU) Field Bits Type Description STEP [9:0] Step Value In Normal Divider Mode, STEP contains the reload value for RESULT. In Fractional Divider Mode, this bit field determines the 10-bit value that is added to RESULT with each input clock cycle.
Page 216 TC1728 System Control Unit (SCU) Field Bits Type Description RESULT [25:16] Result Value In Normal Divider Mode, RESULT acts as reload counter (addition +1). In Fractional Divider Mode, this bit field contains the result of the addition RESULT + STEP.
Page 217: Reset Operation
TC1728 System Control Unit (SCU) Reset Operation This section describes the conditions under which the TC1728 will be reset and the reset operation configuration and control. 3.2.1 Overview The following reset request triggers are available: • 1 External power-on hardware reset request trigger; PORST, (cold reset) •...
Page 218: Reset Sources Overview
Module Reset Behavior Table 3-5 lists how the various functions of the TC1728 are affected through a reset depending on the reset type. A “X” means that this block has at least some register/bits that are affected by this reset.
Page 219: General Reset Operation
TC1728 System Control Unit (SCU) Table 3-5 Effect of Reset on Device Functions Module / Function Application Debug Reset System Power-on Reset Reset Reset CPU Core Peripherals (except SCU) Not affected On-chip OVRAM Not affected, Not affected, Affected, Affected, Static...
Page 220: Reset State Machine
TC1728 System Control Unit (SCU) The duration of a reset is defined by two independent counters. One counter for the Power-on, System, and Application Reset types and one separate counter for the Debug Reset. A separate counter for the Debug Reset was implemented to allow a non- intrusive adaptation of the reset length to the debugger needs without modification of the application setting.
Page 221: Reset Counters (Rstcnta And Rstcntd)
TC1728 System Control Unit (SCU) 3.2.7 Reset Counters (RSTCNTA and RSTCNTD) There are two reset counters implemented. RSTCNTA is the reset counter that controls the reset length for all non debug relevant resets (System Reset and Application Reset). RSTCNTD is the reset counter that controls the reset length for the Debug Reset.
Page 222: De-Assertion Of A Reset
TC1728 System Control Unit (SCU) The reset state of the control block is implemented such that the RSTCNTA is started and two reset types (System and Application) have to be asserted by the distribution logic. The reset state of the control block is implemented such that the RSTCNTD is started and the Debug Reset has to be asserted by the distribution logic.
Page 223: Reset Triggers
TC1728 System Control Unit (SCU) RSTCNTA reached zero the Application Reset is de-asserted when the reset request trigger B is de-asserted. 3.2.9 Reset Triggers There are two types of reset triggers for the reset control logic: • Triggers that lead to a specific reset •...
Page 224: Reset Controller Registers
TC1728 System Control Unit (SCU) 3.2.12 Reset Controller Registers 3.2.12.1 Status Registers After a reset has been executed, the Reset Status registers provide information on the source of the last reset(s). The reset status registers are updated upon each reset cycle.
Page 225 TC1728 System Control Unit (SCU) Field Bits Type Description ESR1 Reset Request Trigger Reset Status for ESR1 The last reset was not requested by this reset trigger The last reset was requested by this reset trigger Note: This bit is set if the ESR1 pin is configured as...
Page 226 TC1728 System Control Unit (SCU) Field Bits Type Description Reset Request Trigger Reset Status for Cerberus System Reset The last reset was not requested by this reset trigger The last reset was requested by this reset trigger Reset Request Trigger Reset Status for Cerberus...
Page 227: Configuration Registers
TC1728 System Control Unit (SCU) Field Bits Type Description Reserved [15:5], Read as 0; should be written with 0. [31:26] 3.2.12.2 Configuration Registers Reset Counter Control Register This register controls the reset length settings for the three resets. RSTCNTCON Reset Counter Control Register...
Page 228 TC1728 System Control Unit (SCU) RSTCON Reset Configuration Register (058 Reset Value: 0000 02A2 ESR1 ESR0 Field Bits Type Description ESR0 [1:0] ESR0 Reset Request Trigger Reset Configuration This bit field defines which reset is generated by a reset request trigger from ESR0 reset.
Page 229 TC1728 System Control Unit (SCU) Field Bits Type Description [7:6] WDT Reset Request Trigger Reset Configuration This bit field defines which reset is generated by a reset request trigger from WDT reset. No reset is generated for a trigger of WDT...
Page 230 TC1728 System Control Unit (SCU) Field Bits Type Description STMDIS STM Disable Reset This bit field defines if an Application Reset leads to an reset for the STM. An Application Reset resets the STM An Application Reset has no effect for the STM...
Page 231 TC1728 System Control Unit (SCU) Field Bits Type Description SWRSTREQ Software Reset Request No SW Reset is requested A SW Reset request trigger is generated This bit is automatically cleared and read always as zero. SWCFG [15:8] Software Boot Configuration...
Page 232: External Interface
TC1728 System Control Unit (SCU) External Interface The SCU provides interface pads for system purpose. Various functions are covered by these pins. Due to the different tasks some of the pads can not be shared with other functions but most of them can. The following functions are covered by the SCU controlled pads: •...
Page 233: Esrx As Reset Output
TC1728 System Control Unit (SCU) In order to be safely recognized ESR0/ESR1 has to be active for a minimum of 2 clock cycles. The input signal ESR0/ESR1 have digital filters (3-stage median filters), that can be disabled. A 3-stage median filter samples with three consecutive clock cycles and the output is defined by the majority of the three sampled values.
Page 234: Esr Registers
TC1728 System Control Unit (SCU) 3.3.1.3 ESR Registers ESRCFG0 ESR0 Configuration Register (070 Reset Value: 0000 0110 ESRCFG1 ESR1 Configuration Register (074 Reset Value: 0000 0090 EDCON Field Bits Type Description DFEN Digital Filter Enable This bit defines if the 3-stage median filter of the ESR0 is used or bypassed.
Page 235 TC1728 System Control Unit (SCU) inputs, and push-pull or open-drain functionality for outputs can be selected by the corresponding bit fields PCx (x = 0-1). IOCR Input/Output Control Register (0A0 Reset Value: 0020 10E0 Field Bits Type Description [7:4] Control for ESR0 Pin...
Page 236 TC1728 System Control Unit (SCU) Pad Control Coding Table 3-9 describes the coding of the PC0 bit field that determine the port line functionality. Table 3-9 PC0 Coding PC0[3:0] Output Selected Pull-up/Pull-down/ Characteristics Selected Output Function 0X00 Input is active and No input pull device connected not inverted;...
Page 237 TC1728 System Control Unit (SCU) Pad Control Coding Table 3-10 describes the coding of the PC1 bit field that determine the port line functionality. Table 3-10 PC1 Coding PC1[3:0] Output Selected Pull-up/Pull-down/ Characteristics Selected Output Function 0X00 Input is active and No input pull device connected not inverted;...
Page 238 TC1728 System Control Unit (SCU) Output Register (0A4 Reset Value: 0000 0000 Field Bits Type Description Output Bit x (x = 0-1) This bit determines the level at the output pin ESRx if the output is selected as GPIO output.
Page 239 TC1728 System Control Unit (SCU) Output Modification Register (0A8 Reset Value: 0000 0000 Field Bits Type Description Set Bit x (x = 0-1) Setting this bit will set or toggle the corresponding bit in the output register OUT. The function of this bit is...
Page 240 TC1728 System Control Unit (SCU) Input Register The logic level of a GPIO pin can be read via the read-only port input register IN. Reading the IN register always returns the current logical value at the GPIO pin independently whether the pin is selected as input or output.
Page 241: External Request Unit (Eru)
The detected events can also be used by other modules to trigger or to gate module- specific actions. 3.3.2.1 Introduction The ERU of the TC1728 can be split in three main functional parts: • 4 independent Input Channels x for input selection and conditioning of trigger or gating functions •...
Page 242 TC1728 System Control Unit (SCU) events (event detected = event flag becomes set, independent of the polarity of the original input signals). • The Connecting Matrix distributes the events and status flags generated by the Input Channels to the Output Channels.
Page 243: Eru Pin Connections
TC1728 System Control Unit (SCU) 3.3.2.2 ERU Pin Connections Figure 3-22 shows the ERU input connections. ERS0 ERS1 P3.10 Input 00 P3.11 Input 10 P0.14 Input 01 P0.15 Input 11 GPTA0_TRIG01 Input 02 P0.11 Input 12 MSC0_FCLP Input 03 Not connected...
Page 244: Event Trigger Logic (Etl)
TC1728 System Control Unit (SCU) Input x0 Input x1 Input channel x Input x2 Input x3 EICRy.EXISx ERU_ERS_block Figure 3-23 External Request Select Unit Overview The ERS unit for channel x is controlled via bit field ERCIy.EXISx. 3.3.2.4 Event Trigger Logic (ETL) For each Input Channel x, an event trigger logic ETLx derives a trigger event and a status from the input channel x delivered by the associated ERSx unit.
Page 245 TC1728 System Control Unit (SCU) EICRm. EICRm. FMR. FMR. FENx LDENx clear clear Modify Status Flag EIFR.INTFx Status to all OGU y EIFR.INTFx Flag Input Detect channel x edge event ERSx Event TRx0 to (edge) OGU0 TRx1 to Enable Select...
Page 246: Connecting Matrix
TC1728 System Control Unit (SCU) 3.3.2.5 Connecting Matrix The connecting matrix distributes the trigger signals (TRxy) and status signals (EIFR.INPFx) from the different ETLx units between the OGUy units. Figure 3-25 provides a complete overview of the connections between the ETLx and the OGUz units.
Page 247 TC1728 System Control Unit (SCU) EIFR .INTF0 Pattern ERU_PDOUT0 Detection TR00 Inputs ERU_GOUT0 TR01 ERU_IOUT0 ETL0 OGU0 TR02 ERU_TOUT0 TR03 Trigger Inputs TRx0 EIFR .INTF1 Pattern ERU_PDOUT1 Detection TR10 Inputs ERU_GOUT1 TR11 ERU_IOUT1 ETL1 OGU1 TR12 ERU_TOUT1 TR13 Trigger Inputs TRx1 EIFR .INTF2...
Page 248: Output Gating Unit (Ogu)
TC1728 System Control Unit (SCU) 3.3.2.6 Output Gating Unit (OGU) Each OGUy unit combines the available trigger events and status flags from the Input Channels and distributes the results to the system. illustrates the logic blocks within an OGUy unit. All functions of an OGUy unit are controlled by the associated IGCRm registers, one for each pair of output channels e.g.
Page 249 TC1728 System Control Unit (SCU) Status Flags EI FR. INTF0 IGCRm. IGCRm. IPENy0 GEENy EI FR. INTF1 ERU_PDOUTy IGCRm. IPENy1 Detect PDRR. Pattern PDRy EI FR. INTF2 IGCRm. Select IPENy2 IGCRm. Gating IGPy EIFR.INTF3 Scheme IGCRm. IPENy3 Triggers from Input...
Page 250 The following table describes the peripheral trigger connections for the OGUy stages. The selection is defined by the bit fields ISS in registers IGCR0 (for OGU0 and OGU1) IGCR1 (for OGU2 and OGU3). Table 3-12 OGUy Peripheral Trigger Connections in TC1728 Input from/to I/O to Can be used to/as Module OGUy...
Page 251 TC1728 System Control Unit (SCU) Table 3-12 OGUy Peripheral Trigger Connections in TC1728 (cont’d) Input from/to I/O to Can be used to/as Module OGUy ERU_ CCU61_SR1 peripheral triggers for OGU1 OGU11 ERU_ Reserved OGU12 ERU_ Reserved OGU13 OGU2 Inputs ERU_...
Page 252: Eru Output Connections
TC1728 System Control Unit (SCU) In addition, the pattern detection can deliver a trigger event if the pattern detection result changes from match to miss or vice-versa (if enabled by IGCRm.GEENy = 1). The pattern result change event is logically OR-combined with the other enabled trigger events to support interrupt generation or to trigger other module functions (e.g.
Page 253 TC1728 System Control Unit (SCU) Table 3-13 ERU Output Connections in TC1728 Output from/to I/O to Can be used to/as Module OGUy OGU0 Outputs ERU_ not connected pattern detection output PDOUT0 ERU_ not connected gated pattern detection output GOUT0 ERU_...
Page 254: External Request Unit Registers
TC1728 System Control Unit (SCU) Table 3-13 ERU Output Connections in TC1728 (cont’d) Output from/to I/O to Can be used to/as Module OGUy ERU_ Interrupt Generation interrupt output IOUT2 DMA channel 02 DMA channel 06 ADC trigger input FADC input FADC_TSC...
Page 255 TC1728 System Control Unit (SCU) EICR0 External Input Channel Register 0 (080 Reset Value: 0000 0000 INP1 EXIS1 INP0 EXIS0 Field Bits Type Description EXIS0 [5:4] External Input Selection 0 This bit field determines which input line is selected for Input Channel 0.
Page 256 TC1728 System Control Unit (SCU) Field Bits Type Description LDEN0 Level Detection Enable 0 This bit determines if bit INTF0 is cleared automatically if an edge of the input Input Channel 0 is detected, which has not been selected (rising edge with REN0 = 0 or falling edge with FEN0 = 0).
Page 257 TC1728 System Control Unit (SCU) Field Bits Type Description FEN1 Falling Edge Enable 1 This bit determines if the falling edge of Input Channel 1 is used to set bit INTF1. The falling edge is not used The detection of a falling edge of Input Channel...
Page 258 TC1728 System Control Unit (SCU) Field Bits Type Description INP1 [30:28] Input Node Pointer This bit field determines the destination (output channel) for trigger event 1 (if enabled by EIEN1). The event of input channel 1 triggers output channel 0 (signal INT10)
Page 259 TC1728 System Control Unit (SCU) Field Bits Type Description EXIS2 [5:4] External Input Selection 2 This bit field determines which input line is selected for Input Channel 2. Input 20 is selected Input 21 is selected Input 22 is selected...
Page 260 TC1728 System Control Unit (SCU) Field Bits Type Description INP2 [14:12] Input Node Pointer This bit field determines the destination (output channel) for trigger event 2 (if enabled by EIEN2). The event of input channel 2 triggers output channel 0 (signal INT20)
Page 261 TC1728 System Control Unit (SCU) Field Bits Type Description LDEN3 Level Detection Enable 3 This bit determines if bit INTF3 is cleared automatically if an edge of the input Input Channel 3 is detected, which has not been selected (rising edge with REN3 = 0 or falling edge with FEN3 = 0).
Page 262 TC1728 System Control Unit (SCU) EIFR External Input Flag Register (088 Reset Value: 0000 0000 Field Bits Type Description INTFx External Interrupt Flag of Channel x (x = 0-3) This bit monitors the status flag of the event trigger condition for the input channel x. This bit is...
Page 263 TC1728 System Control Unit (SCU) Field Bits Type Description Set Flag INTFx for Channel x (x = 0-3) Setting this bit will set the corresponding bit INTFx in register EIFR. Reading this bit always delivers a 0. The bit x in register EIFR is not modified...
Page 264 TC1728 System Control Unit (SCU) The Interrupt Gating Control Registers IGCR0 and IGCR1 contain bits to enable the pattern detection and to control the gating for output channel 0 to 3. IGCR0 Interrupt Gating Register 0 (094 Reset Value: 0000 0000...
Page 265 TC1728 System Control Unit (SCU) Field Bits Type Description GEEN0 Generate Event Enable 0 Bit GEEN0 enables the generation of a trigger event for output channel 0 when the result of the pattern detection changes. When using this feature, a trigger (e.g.
Page 266 TC1728 System Control Unit (SCU) Field Bits Type Description IPEN1x 16+x Interrupt Pattern Enable for Channel 1 (x = 0-3) Bit IPEN1x determines if the flag INTFx of channel x takes part in the pattern detection for the gating of the requests for the output signals GOUTy and IOUTy.
Page 267 TC1728 System Control Unit (SCU) IGCR1 Interrupt Gating Register 1 (098 Reset Value: 0000 0000 IPEN IPEN IPEN IPEN IGP3 ISS3 IPEN IPEN IPEN IPEN IGP2 ISS2 Field Bits Type Description IPEN2x Interrupt Pattern Enable for Channel 2 (x = 0-3)
Page 268 TC1728 System Control Unit (SCU) Field Bits Type Description GEEN2 Generate Event Enable 2 Bit GEEN2 enables the generation of a trigger event for output channel 2 when the result of the pattern detection changes. When using this feature, a trigger (e.g.
Page 269 TC1728 System Control Unit (SCU) Field Bits Type Description ISS3 [25:24] Internal Trigger Source Selection This bit field defines which input is selected as peripheral trigger input for OGU13. The possible input signals are given in Table 3-13. The peripheral trigger function is disabled...
Page 270: Power Supply And Control
Power Supply and Control 3.4.1 Basic Operation The TC1728 can run from a single external power supply. The pad and core supply voltages can be generated by on-chip Embedded Voltage Regulators (EVRs) or can be provided externally. The following figures show the different supply options beside that all voltages are provided externally.
Page 271 TC1728 System Control Unit (SCU) AREFx AGNDx supply FAREF DDMF EVR_33 DDPF3 DDLF3 DDOSC3 EVR_13 DDPF DDAF DDOSC power_supply _172 x Figure 3-28 Basic EVR concept for 5V supply without Pass Device User’s Manual 3-116 V1.0, 2011-12 32-bit Platform SCU, V1.0...
Page 272 TC1728 System Control Unit (SCU) AREFx AGNDx 3.3 V supply FAREF DDMF EVR_33 DDPF3 DDLF3 DDOSC3 EVR_13 DDPF DDAF DDOSC power _supply _172x Figure 3-29 Basic EVR concept for 3.3V supply with Pass Device User’s Manual 3-117 V1.0, 2011-12 32-bit Platform SCU, V1.0...
Page 273 Figure 3-30 Basic EVR concept for 3.3V supply without Pass Device The basic power supply concept of the TC1728 implies of a single external 5 V power supply source and two cascaded EVRs. All required supply voltages beside the ADC...
Page 274: Enhanced Reset System
TC1728 System Control Unit (SCU) 3.4.2 Enhanced Reset System The existing reset system is only enhanced and not changed. Adaptation is only done where the EVR introduction itself generates new requirements. The PORST pin needs to be a bidirectional reset in/output for power related resets. This is not replacement for the ESR pins transporting the functional reset information.
Page 275 TC1728 System Control Unit (SCU) When the EVR33 reaches its active level the EVR13 is started. When this EVR also reaches the active level the system is ready for operation and the normal start-up is started. 3.3 V External Supply Only Here the EVR33 is not required for the supply concept.
Page 276: Evr Control Registers
TC1728 System Control Unit (SCU) 3.4.4 EVR Control Registers EVRRSTCON EVR Reset Control Register (06C Reset Value: 10C9 86C7 ST33 ST13 RST50TRIM RST33TRIM RST13TRIM Field Bits Type Description RST13TRIM [7:0] 1.3 V Regulator Reset Trim Value This bit field selects the reset generation level of the EVR13.
Page 277 TC1728 System Control Unit (SCU) Field Bits Type Description RST33OFF Reset EVR33 Off A reset trigger signal is generaterd and forward to the SCU by the EVR33 block depending on the selected reset trim value No reset trigger signal is generaterd and...
Page 278: Power Management
TC1728 System Control Unit (SCU) Power Management This section describes the power management system of the TC1728. Topics covered here include the internal system interfaces, external interfaces, and the operations of the CPU and peripherals. 3.5.1 Power Management Overview The TC1728 power-management system allows software to configure the various processing units so that they automatically adjust to draw the minimum necessary power for the application.
Page 279: Power Management Modes
If any of these conditions arise, the TC1728 immediately awakens and returns to Run Mode. If it is awakened by a reset, the TC1728 system begins its reset sequence. If it is awakened by a Watchdog Timer overflow event, it executes the instruction following the one that was last executed before Idle Mode was entered.
Page 280: Sleep Mode
Sleep Mode will switch back to their selected Run Mode operation. 3.5.3 Power Management Control and Status Register, PMCSR The set of registers used for power management is divided between central TC1728 components and peripheral components. The PMCSR register provides software control User’s Manual 3-125 V1.0, 2011-12...
Page 281 Sleep Mode behavior of each peripheral component is programmable. When entering Idle Mode and Sleep Mode, the Power Management directly controls TC1728 components such as the CPU, but indirectly controls peripheral components through their clock control registers.
Page 282 TC1728 System Control Unit (SCU) Field Bits Type Function [7:2], Reserved [31:11] Read as 0; should be written with 0. User’s Manual 3-127 V1.0, 2011-12 32-bit Platform SCU, V1.0...
Page 283: Software Boot Support
TC1728 System Control Unit (SCU) Software Boot Support In order to determine the correct starting point of operation for the software a minimum of hardware support is required. As much as possible is done via software. Some decisions have to be done in hardware because they must be known before any software is operational.
Page 284: Start-Up Registers
TC1728 System Control Unit (SCU) 3.6.3 Start-up Registers 3.6.3.1 Start-up Status Register Register STSTAT contains the information required by the boot software to identify the different start-up settings that can be selected. STSTAT Start-up Status Register (0C0 Reset Value: 0000 8000...
Page 285 TC1728 System Control Unit (SCU) Field Bits Type Description Mode Mode This bit indicates if the Test Mode is entered or not. A Test Mode can be selected Normal Mode is selected FCBAE Flash Config. Sector Access Enable Flash config sector is not accessible. Instead the flash memory area is accessed.
Page 286 TC1728 System Control Unit (SCU) STCON Start-up Configuration Register (0C4 Reset Value: 0000 8000 HWCFG Field Bits Type Description HWCFG [7:0] Hardware Configuration Setting Writing to this bit field updates bit field STSTAT.HWCFG. Reading this bit field returns zero. SFCBAE Set Flash Config.
Page 287: Ecc Error Handling
TC1728 System Control Unit (SCU) ECC Error Handling The on-chip RAM and flash modules check ECC information during read accesses and in case of an error a signal is generated. These signals are combined and trigger a trap. clear ECCCLR.
Page 288: Ecc Registers
TC1728 System Control Unit (SCU) 3.7.2 ECC Registers ECCCON ECC Control Register (0D0 Reset Value: 0000 FFFF Field Bits Type Description ECCENLDRA ECC Error Trap Enable for LDRAM and DCACHE Memory This bit determine whether a trap is requested if an uncorrected ECC error is detected in the LDRAM / DCACHE memory.
Page 289 TC1728 System Control Unit (SCU) Field Bits Type Description ECCENPTAG ECC Error Trap Enable for Program Cache TAG RAM Memory This bit determine whether a trap is requested if an uncorrected ECC error is detected in the program cache TAG RAM memory.
Page 290 TC1728 System Control Unit (SCU) Field Bits Type Description ECCENLMB ECC Error Trap Enable for LMB This bit determine whether a trap is requested if an uncorrected ECC error is detected by the LMB. No ECC error trap trigger is requested...
Page 291 TC1728 System Control Unit (SCU) Field Bits Type Description DTAG ECC Error Flag for Data Cache TAG RAM Memory This bit indicate whether an ECC error has been detected in the data TAG RAM memory. No ECC error detected ECC error is detected...
Page 292 TC1728 System Control Unit (SCU) Field Bits Type Description ERAY ECC Error Flag for ERAY Memory This bit indicate whether an ECC error has been detected in the ERAY memory. No ECC error detected ECC error is detected ECC Error Flag for LMB-Bus This bit indicate whether an ECC error has been detected in the LMB-Bus.
Page 293 TC1728 System Control Unit (SCU) Field Bits Type Description DTAG Clear Data Cache TAG RAM ECC Error Status No action Setting this bit clears bit ECCSTAT.DTAG This bit always read as 0. SPRAM Clear SPRAM and ICACHE ECC Error Status No action Setting this bit clears bit ECCSTAT.SPRAM...
Page 294 TC1728 System Control Unit (SCU) Field Bits Type Description Clear BMU Memory ECC Error Status No action Setting this bit clears bit ECCSTAT.BMU This bit always read as 0. Reserved [31:12] Read as 0; should be written with 0. User’s Manual 3-139 V1.0, 2011-12...
Page 295: Watchdog Timer
The WDT provides a highly reliable and secure way to detect and recover from software or hardware failure. The WDT helps to abort an accidental malfunction of the TC1728 in a user-specified time period. When enabled, the WDT can cause the TC1728 system to be reset if the WDT is not serviced within a user-programmable time period.
Page 296: The Endinit Function
Hence, its function is explained first. There are a number of registers in the TC1728 that are usually programmed only once during the initialization sequence of the application. Modification of such registers during normal application run can have a severe impact on the overall operation of modules or the entire system.
Page 297 As a solution, WDT_CON0 (the register with the ENDINIT bit) should be read back once before Endinit-protected registers are accessed the first time after bit ENDINIT has been cleared. Table 3-17 TC1728 Registers Protected via the Endinit Feature Register Name Description mod_CLC...
Page 298: Password Access To Wdt_Con0
TC1728 System Control Unit (SCU) Table 3-17 TC1728 Registers Protected via the Endinit Feature (cont’d) Register Name Description SCU_TRAPSET The trap set and disable register SCU_TRAPDIS Px_ESR Port Control Registers Px_PDR DMA_MExARR DMA Control Registers DMA_MExAENR DMA_OCDSR DMA_SUSPMR PCP_CS PCP Control Registers...
Page 299: Modify Access To Wdt_Con0
TC1728 System Control Unit (SCU) If the password matches the requirements, WDT_CON0 will be unlocked as soon as the Password Access is completed. The unlocked condition will be indicated by WDT_CON0.LCK = 0. If an improper password value is written to WDT_CON0 during the Password Access, a Watchdog Access Error condition exists.
Page 300: Timer Operation
TC1728 System Control Unit (SCU) ENDINIT can be cleared. Access to Endinit-protected registers is now open again. However, when WDT_CON0 is unlocked, the WDT is automatically switched to Time- Out Mode. Thus, the access window is time-limited. Time-Out Mode is only terminated after ENDINIT has been set again, requiring another Valid Password and Valid Modify Access to WDT_CON0.
Page 301 TC1728 System Control Unit (SCU) The following overview describes these modes and how the WDT changes from one mode to the other. Time-Out Mode The Time-Out Mode is entered after an Application Reset or when a valid Password Access to register WDT_CON0 is performed (see Section 3.8.3.1).
Page 302: Wdt Reset Behavior
If the Watchdog induced reset occurs twice, a severe system malfunction is assumed and the TC1728 is held in reset until a System Reset occurs. This prevents the device from being periodically reset if, for instance, connection to the external memory has been lost such that even system initialization could not be performed.
Page 303: Wdt Operation During Power-Saving Modes
TC1728 System Control Unit (SCU) Note: It does not matter whether a reset was generated on a WDT reset request or if the reset configuration was changed between the two reset requests. Note: If for any reason random code is executed bit field RSTCON.WDT can be updated unintentional.
Page 304: Suspend Mode Support
TC1728 System Control Unit (SCU) Note: Before switching into a non-running power-management mode, software should perform a Watchdog service sequence. At the Modify Access, the Watchdog reload value, WDT_CON0.REL, should be programmed such that the wake-up occurs after a period which best meets application requirements. The maximum period between two CPU wake-ups is one-half of the maximum WDT period.
Page 305 TC1728 System Control Unit (SCU) WDT_CON0 WDT Control Register 0 (F000 05F0 Reset Value: FFFC 0002 HPW1 HPW0 INIT Field Bits Type Description ENDINIT End-of-Initialization Control Bit Access to Endinit-protected registers is permitted (default after Application Reset) Access to Endinit-protected registers is not...
Page 306: Watchdog Timer Control Register 1
TC1728 System Control Unit (SCU) Field Bits Type Description HPW0 [3:2] Hardware Password 0 This bit field must be written with the value of the bits WDT_CON1.DR and WDT_CON1.IR during a Password Access. This bit field must be written with 0s during a Modify Access to WDT_CON0.
Page 307 TC1728 System Control Unit (SCU) WDT_CON1 WDT Control Register 1 (F000 05F4 Reset Value: 0000 0000 Field Bits Type Description CLRIRF Clear Internal Reset Flag This bit is used to request a clear of the internal flag storing the information about the first WDT reset request.
Page 308: Watchdog Timer Status Register
TC1728 System Control Unit (SCU) Field Bits Type Description Disable Request Control Bit Request to enable the WDT Request to disable the WDT This bit can only be modified if WDT_CON0.ENDINIT is cleared. WDT_SR.DS is updated when ENDINIT is set again. As long as ENDINIT is cleared, bit WDT_SR.DS controls the current enable/disable...
Page 309 TC1728 System Control Unit (SCU) Field Bits Type Description Watchdog Access Error Status Flag No Watchdog access error A Watchdog access error has occurred This bit is set when an illegal Password Access or Modify Access to register WDT_CON0 was attempted.
Page 310 TC1728 System Control Unit (SCU) Field Bits Type Description Watchdog Time-Out Mode Flag The Watchdog is not operating in Time-Out Mode The Watchdog is operating in Time-Out Mode (default after Application Reset) This bit is set when Time-Out Mode is entered. It is automatically cleared when Time-Out Mode is left.
Page 311: Emergency Stop Output Control
System Control Unit (SCU) Emergency Stop Output Control The emergency stop feature of the TC1728 allows for a fast emergency reaction on an external event without the intervention of software. In an emergency case, the outputs can be selectively put immediately to a well-defined logic state (for more information see the port chapter).
Page 312: Emergency Stop Register
TC1728 System Control Unit (SCU) 3.9.1 Emergency Stop Register The Emergency Stop Register EMSR contains control and status bits/flags of the emergency stop input logic. EMSR Emergency Stop Register (100 Reset Value: 0000 0000 EMSFM Field Bits Type Description Input Polarity This bit determines the polarity of the input line.
Page 313 TC1728 System Control Unit (SCU) Field Bits Type Description EMSF Emergency Stop Flag This bit indicates if an emergency stop condition has occurred. An emergency stop has not occurred An emergency stop has occurred and signal emergency stop becomes active (if MODE = 0)
Page 314: Interrupt Generation
TC1728 System Control Unit (SCU) 3.10 Interrupt Generation The interrupt structure is shown in Figure 3-32. The interrupt request or the corresponding interrupt set bit (in register INTSET) can trigger the interrupt generation at the selected interrupt node x. The service request pulse is generated independently from the interrupt flag in register INTSTAT.
Page 315: Interrupt Control Registers
TC1728 System Control Unit (SCU) 3.10.1 Interrupt Control Registers INTSTAT Interrupt Status Register (110 Reset Value: 0000 0000 ERUI ERUI ERUI ERUI FL0I Field Bits Type Description WDTI Watchdog Timer Interrupt Request Flag This bit is set if the WDT Prewarning Mode is entered and bit is INTDIS.WDTI = 0.
Page 316 TC1728 System Control Unit (SCU) Field Bits Type Description ERUI1 ERU Channel 1 Interrupt Request Flag This bit is set if the ERU channel 1 is active and bit is INTDIS.ERUI1 = 0. No interrupt was requested since this bit was...
Page 317 TC1728 System Control Unit (SCU) Field Bits Type Description [15:6] Reserved Read as 0. This bit can be cleared by bit INTCLR.[x]. This bit can be set by bit INTSET.[x]. Note: x = 6, [13:8], 15. [31:16] r Reserved Read as 0; should be written with 0.
Page 318 TC1728 System Control Unit (SCU) Field Bits Type Description ERUI2 Set Interrupt Request Flag ERUI2 Setting this bit set bit INTSTAT.ERUI2. Clearing this bit has no effect. Reading this bit returns always zero. ERUI3 Set Interrupt Request Flag ERUI3 Setting this bit set bit INTSTAT.ERUI3.
Page 319 TC1728 System Control Unit (SCU) Field Bits Type Description ERUI0 Clear Interrupt Request Flag ERUI0 Setting this bit clears bit INTSTAT.ERUI0. Clearing this bit has no effect. Reading this bit returns always zero. ERUI1 Clear Interrupt Request Flag ERUI1 Setting this bit clears bit INTSTAT.ERUI1.
Page 320 TC1728 System Control Unit (SCU) Field Bits Type Description WDTI Disable Interrupt Request WDT An interrupt request can be generated for this source No interrupt request can be generated for this source ERUI0 Disable Interrupt Request ERU0 An interrupt request can be generated for this...
Page 321 TC1728 System Control Unit (SCU) INTNP Interrupt Node Pointer Register (120 Reset Value: 0000 0000 ERU3 ERU2 ERU1 ERU0 Field Bits Type Description [1:0] Interrupt Node Pointer for Interrupt WDT This bit field defines the interrupt node, that is requested due to the set condition for bit INTSTAT.WDTI (if enabled by bit INTDIS.WDTI).
Page 322 TC1728 System Control Unit (SCU) Field Bits Type Description ERU2 [7:6] Interrupt Node Pointer for Interrupt ERU2 This bit field defines the interrupt node, that is requested due to the set condition for bit INTSTAT.ERUI2 (if enabled by bit INTDIS.ERUI2).
Page 323 TC1728 System Control Unit (SCU) SRC0 Service Request Control 0 Register (1FC Reset Value: 0000 0000 SRC1 Service Request Control 1 Register (1F8 Reset Value: 0000 0000 SRC2 Service Request Control 2 Register (1F4 Reset Value: 0000 0000 SRC3 Service Request Control 3 Register...
Page 324 TC1728 System Control Unit (SCU) Field Bits Type Description SETR Request Set Bit SETR is required to set SRR. No action Set SRR; bit value is not stored; read always returns 0; no action if CLRR is set also. [9:8], 11,...
Page 325: Nmi Trap Generation
TC1728 System Control Unit (SCU) 3.11 NMI Trap Generation The NMI trap structure is shown in Figure 3-33. The trap request trigger or the corresponding trap set bit (in register TRAPSET) can trigger the NMI trap generation. The trap flag can be cleared by software by writing to the corresponding bit in register TRAPCLR.
Page 326: Trap Control Registers
TC1728 System Control Unit (SCU) 3.11.1 Trap Control Registers TRAPSTAT Trap Status Register (124 Reset Value: 0000 0000 Field Bits Type Description ESR0T ESR0 Trap Request Flag This bit is set if an ESR0 event is triggered and bit is TRAPDIS.ESR0T is cleared.
Page 327 TC1728 System Control Unit (SCU) Field Bits Type Description WDTT WDT Trap Request Flag This bit is set if a WDT trap is indicated and bit is TRAPDIS.WDTT is cleared. No trap was requested since this bit was cleared the last time...
Page 328 TC1728 System Control Unit (SCU) Field Bits Type Description OSCHWDTT OSCWDT High Trap Request Flag This bit is set if a oscillator WDT of the PLL detects a high event and bit is TRAPDIS.OSCHWDTT cleared. No trap was requested since this bit was...
Page 329 TC1728 System Control Unit (SCU) Field Bits Type Description [31:16] r Reserved Read as 0; should be written with 0. TRAPSET Trap Set Register (128 Reset Value: 0000 0000 Field Bits Type Description ESR0T Set Trap Request Flag ESR0T Setting this bit set bit TRAPSTAT.ESR0T.
Page 330 TC1728 System Control Unit (SCU) Field Bits Type Description OSCLWDTT Set Trap Request Flag OSCLWDTT Setting this bit set bit TRAPSTAT.OSCLWDTT. Clearing this bit has no effect. Reading this bit returns always zero. OSCHWDTT Set Trap Request Flag OSCHWDTT Setting this bit set bit TRAPSTAT.OSCHWDTT.
Page 331 TC1728 System Control Unit (SCU) Field Bits Type Description ESR0T Clear Trap Request Flag ESR0T Setting this bit clears bit TRAPSTAT.ESR0T. Clearing this bit has no effect. Reading this bit returns always zero. ESR1T Clear Trap Request Flag ESR1T Setting this bit clears bit TRAPSTAT.ESR1T.
Page 332 TC1728 System Control Unit (SCU) TRAPDIS Trap Disable Register (130 Reset Value: 0000 FFFF Field Bits Type Description ESR0T Disable Trap Request ESR0T A trap request can be generated for this source No trap request can be generated for this...
Page 333 TC1728 System Control Unit (SCU) Field Bits Type Description OSCHWDTT Disable Trap Request OSCHWDTT A trap request can be generated for this source No trap request can be generated for this source OSCSPWDTT 7 Disable Trap Request OSCSPWDTT A trap request can be generated for this source...
Page 334: Miscellaneous System Control Register
3.12.1 GPTA Input IN1 Control In the TC1728, the input line IN1 of the GPTA module can be used to measure the baud rate of an ASC0 or ASC1 receiver input signal with GPTA. This feature is controlled by SYSCON.GPTAIS.
Page 335 TC1728 System Control Unit (SCU) SYSCON System Control Register (040 Reset Value: 0000 0000 GPTAIS RIG0 Field Bits Type Description CCTRIG0 Capture Compare Trigger 0 This bit is used to trigger the Synchronous Start feature of the CAPCOMs in the system.
Page 336: Identification Registers
Type Description CHREV [7:0] Chip Revision Number This bit field indicates the revision number of the TC1728 device. The value of this bit field is defined in the TC1728 Data Sheet. CHID [15:8] Chip Identification Number This bit field defines the product by a unique number.
Page 337 MODREV Field Bits Type Description MODREV [7:0] Module Revision Number This bit field indicates the revision number of the TC1728 module (01 = first revision). MODTYPE [15:8] Module Type This bit field is C0 . It defines a 32-bit module...
Page 338 Bits Type Description DEPT [4:0] Department Identification Number = 00 : indicates the Automotive & Industrial microcontroller department within Infineon Technologies. MANUF [15:5] Manufacturer Identification Number This is a JEDEC normalized manufacturer code. MANUF = C1 stands for Infineon Technologies.
Page 339: Scu Kernel Registers
This section describes the kernel registers of the 32-bit Platform SCU module. Most of 32-bit Platform SCU kernel register names described in this section will be referenced in other parts of the TC1728 User’s Manual by the module name prefix “SCU_”. SCU Kernel Register Overview...
Page 340 TC1728 System Control Unit (SCU) Table 3-22 Register Overview of SCU Short Long Name Offset Access Mode Reset Description Name Addr. Read Write PLLERAY PLL_ERAY U, SV SV, E System Page 3-37 CON0 Configuration 0 Reset Register PLLERAY PLL_ERAY U, SV...
Page 341 TC1728 System Control Unit (SCU) Table 3-22 Register Overview of SCU Short Long Name Offset Access Mode Reset Description Name Addr. Read Write ESRCFG0 ESR0 U, SV SV, E System Page 3-79 Configuration Reset Register ESRCFG1 ESR1 U, SV SV, E...
Page 342 TC1728 System Control Unit (SCU) Table 3-22 Register Overview of SCU Short Long Name Offset Access Mode Reset Description Name Addr. Read Write PMCSR Power U, SV U, SV Application Page 3-126 Management Reset Control and Status Register – Reserved –...
Page 343 TC1728 System Control Unit (SCU) Table 3-22 Register Overview of SCU Short Long Name Offset Access Mode Reset Description Name Addr. Read Write INTSET Interrupt Set U, SV U, SV Application Page 3-162 Register Reset INTCLR Interrupt Clear U, SV...
Page 344 TC1728 System Control Unit (SCU) Table 3-22 Register Overview of SCU Short Long Name Offset Access Mode Reset Description Name Addr. Read Write SRC1 Service Request U, SV Application Page 3-168 Control Register 1 Reset SRC0 Service Request U, SV...
Page 345: Scu Address Area
TC1728 System Control Unit (SCU) 3.12.5 SCU Address Area Table 3-23 Registers Address Space - SCU Kernel Registers Module Base Address End Address Note F000 0500 F000 06FF User’s Manual 3-190 V1.0, 2011-12 32-bit Platform SCU, V1.0...
Page 346: On-Chip System Buses And Bus Bridges
TC1728 On-Chip System Buses and Bus Bridges On-Chip System Buses and Bus Bridges The TC1728 has two independent on-chip buses: • Local Memory Bus (LMB) • System Peripheral Bus (SPB) Floating Point Unit TriCore 116 KB LDRAM 16 KB SPRAM...
Page 347: What Is New
Major differences of the AudoFuture On Chip Bus System architecture compared to AudoNG: • The TC1728 is based on two on chip busses (LMB, SPB). The remote peripheral bus (RPB) was removed. • The DMA is additionally connected to the LMB bus with a master interface.
Page 348: Local Memory Bus
TC1728 On-Chip System Buses and Bus Bridges Local Memory Bus The following terminology is used for the bus: Table 4-1 LMB Bus Terms Term Description Agent An LMB agent is any master or slave device which is connected to the LMB Bus.
Page 349: Block Transfers
TC1728 On-Chip System Buses and Bus Bridges 4.2.2.2 Block Transfers Block transfers are only issued in the following ways: 1. By the PMI and DMI in case of a cache miss. 2. By the PCP if it uses a BCOPY instruction.
Page 350: Lmb Basic Operation
TC1728 On-Chip System Buses and Bus Bridges 4.2.5 LMB Basic Operation Figure 4-2 describes some basic bus operations of the LMB. Bus Cycle Request/ Address Data Transfer 1 Grant Cycle Cycle Request/ Address Data Transfer 2 Grant Cycle Cycle Address...
Page 351: Local Memory Bus Controller Unit
TC1728 On-Chip System Buses and Bus Bridges Local Memory Bus Controller Unit The LMB in the TC1728 has an LMB Bus Control Unit (LBCU). 4.3.1 Basic Operation The LBCU handles the cycle sequences of the transfers which have been requested by the LMB master devices.
Page 352: Lmb Bus Default Master
TC1728 On-Chip System Buses and Bus Bridges 4.3.2.1 LMB Bus Default Master When no LMB master is requesting the LMB, it is granted to the LMB default master. This means, if the default master needs the LMB in the next cycle, it can enter the address cycle without running through a request/grant cycle.
Page 353: Lmb Bus Control Unit Registers
TC1728 On-Chip System Buses and Bus Bridges 4.3.4 LMB Bus Control Unit Registers Figure 4-4 Table 4-4 are showing the address maps with all registers of LMB Bus Control Unit (LBCU) module. LBCU Unit Register Overview Identification Control Registers Address/Data...
Page 354 TC1728 On-Chip System Buses and Bus Bridges Table 4-4 Registers Overview - LBCU Module Control Registers Short Description Offset Access Mode Reset Description Name Addr. Class Read Write LBCU_LE LBCU LMB Error Data Page 4-15 DATL Low Register LBCU_LE LBCU LMB Error Data...
Page 355 TC1728 On-Chip System Buses and Bus Bridges Table 4-4 Registers Overview - LBCU Module Control Registers Short Description Offset Access Mode Reset Description Name Addr. Class Read Write Reserved LBCU_SR LBCU Service Request SV, 32 3 Page 4-23 Control Register...
Page 356: Lmb Bus Control Unit Control Registers
TC1728 On-Chip System Buses and Bus Bridges 4.3.4.1 LMB Bus Control Unit Control Registers The identification register allows the programmer version-tracking of the module. The table below shows the identification register which is implemented in the LBCU module. LBCU_ID Module Identification Register...
Page 357 TC1728 On-Chip System Buses and Bus Bridges LBCU_LEATT LBCU LMB Error Attribute Register (020 Reset Value: XXXX XXX0 WR SVM LOC NOS ABT FPITAG Field Bits Type Description Lock Error Capture This bit indicates and controls whether the error- capture mechanism is unlocked or locked.
Page 358 TC1728 On-Chip System Buses and Bus Bridges Field Bits Type Description FPITAG [7:4] FPI Bus Master TAG This bit field indicates the FPI Bus master tag in case of an LMB bus error. Note that the FPI Bus master tag is only of interest if the erroneous LMB transfer was initiated by the DMA or the PCP..
Page 359 TC1728 On-Chip System Buses and Bus Bridges Field Bits Type Description LMB Bus Write Error Indication This bit indicates whether the LMB bus error occurred at a write cycle (see Table 4-5). LMB Bus Read Error Indication This bit indicates whether the LMB bus error...
Page 360 TC1728 On-Chip System Buses and Bus Bridges Table 4-5 LMB Bus Read/Write Error Indication (cont’d) LMB Bus Cycle LMB bus error occurred at a write cycle of a single transfer or at the write cycle of an atomic transfer. Does not occur.
Page 361 TC1728 On-Chip System Buses and Bus Bridges LBCU_LEDATH LBCU LMB Error Data High Register (02C Reset Value: XXXX XXXX LEDAT[63:32] Field Bits Type Description LEDAT[63:32] [31:0] LMB Bus Address Bits [31:0] This bit field holds the upper 32-bit part of the 64-bit LMB data that has been captured at an LMB bus error.
Page 362 TC1728 On-Chip System Buses and Bus Bridges LBCU_LEDATED LMB Error Data Error Detection Register (038 Reset Value: 0000 00XX DATA_ED Field Bits Type Description DATA_ED [7:0] LMB Error Data Error Detection LMB data Error Detection information captured during erroring transaction.
Page 363 TC1728 On-Chip System Buses and Bus Bridges Field Bits Type Description [31:5] Reserved Read as 0. LBCU_LSEADS LMB Soft Error Address Source Register (040 Reset Value: 0000 XXXX LMB_Module Field Bits Type Description LMB_Module [15:0] LMB Soft Error Address Source LMB modules that indicated an error in the address phase of the current transaction.
Page 364 TC1728 On-Chip System Buses and Bus Bridges LBCU_LSEABS LMB Soft Error Abort Source Register (044 Reset Value: 0000 XXXX LMB_Module Field Bits Type Description LMB_Module [15:0] LMB Soft Error Abort Source LMB modules that indicated an error in the abort phase of the current transaction.
Page 365 TC1728 On-Chip System Buses and Bus Bridges LBCU_LSERDS LMB Soft Error Read Source Register (048 Reset Value: 0000 XXXX LMB_Module Field Bits Type Description LMB_Module [15:0] LMB Soft Error Read Source LMB modules that indicated an error in the read data phase of the current transaction.
Page 366 TC1728 On-Chip System Buses and Bus Bridges LBCU_LSEWRS LMB Soft Error Write Source Register (04C Reset Value: 0000 XXXX LMB_Module Field Bits Type Description LMB_Module [15:0] LMB Soft Error Write Source LMB modules that indicated an error in the write data phase of the current transaction.
Page 367 TC1728 On-Chip System Buses and Bus Bridges LBCU_LSERES LMB Soft Error Response Register (050 Reset Value: 0000 XXXX LMB_Module Field Bits Type Description LMB_Module [15:0] LMB Soft Error Abort Source LMB modules that indicated an error in the acknowledge phase of the current transaction.
Page 368 TC1728 On-Chip System Buses and Bus Bridges LBCU_SRC LBCU Service Request Control Register (0FC Reset Value: 0000 0000 SRR SRE SRPN Field Bits Type Description SRPN [7:0] Service Request Priority Number [11:10] r Type-of-Service State Always read as 00 . This means type-of-service is associated with interrupt bus 0 (CPU interrupt arbitration bus).
Page 369: Local Memory Bus To Fpi Bus Interface (Lfi Bridge)
TC1728 On-Chip System Buses and Bus Bridges Local Memory Bus to FPI Bus Interface (LFI Bridge) This section describes the basic functionality of the LFI Bridge. 4.4.1 Functional Overview The LFI Bridge is a bi-directional bus bridge between the LMB and the System Peripheral FPI Bus (SPB).
Page 370 TC1728 On-Chip System Buses and Bus Bridges Note that this behavior occurs only at write operations via the LFI Bridge. It can also be triggered by an erroneous write cycle of a read-modify-write bus transaction. User’s Manual 4-25 V1.0, 2011-12...
Page 371: Lmb To Fpi Bridge Control Registers
TC1728 On-Chip System Buses and Bus Bridges 4.4.2 LMB to FPI Bridge Control Registers Table 4-7 Table 4-8 are showing the address maps with all registers of the LMB to FPI Bridge (LFI) module. LFI Register Identification Register LFI_ID LFI_CON...
Page 372: Lfi Register Description
TC1728 On-Chip System Buses and Bus Bridges 2) Read as 0. Should not be written. If it is written, it must be written with 0. 4.4.2.1 LFI Register Description The identification register allows the programmer version-tracking of the module. The table below shows the identification register which is implemented in the LFI module.
Page 373 Returns 0 if read; must be written with 0. LTAG [6:4] LMB Bus Tag ID In the TC1728, the bit field LTAG = 000 FTAG [11:8] FPI Bus (SPB) Tag ID In the TC1728, the bit field FTAG = 1011 , which reflects the tag number of the LFI Bridge on the SPB.
Page 374: System Peripheral Bus
• Support of atomic operations LDMST, ST.T and SWAP.W The functional units of the TC1728 are connected to the FPI Bus via FPI Bus interfaces. An FPI Bus interfaces acts as bus agents, requesting bus transactions on behalf of their functional unit, or responding to bus transaction requests.
Page 375 Some functional units operate only as slaves, while others can operate as either masters or slaves on the FPI Bus. In the TC1728, DMI and PMI (via the LFI Bridge), PCP and DMA (including Cerberus and MLI´s) operate as FPI Bus masters. On-chip peripheral units are typically FPI Bus slaves.
Page 376: Bus Transaction Types
2 word, 4 word, or 8 word transfers. Note: In general, block transfers (2 word, 4 word, or 8 word) cannot be executed in the TC1728 with peripheral units that operate as FPI Bus slaves during an FPI Bus transaction.
Page 377: Address Alignment Rules
TC1728 On-Chip System Buses and Bus Bridges 4.5.4 Address Alignment Rules FPI Bus address generation is compliant with the following rules: • Half-word transactions must have a half-word aligned address (A0 = 0). Half-word accesses on byte lanes 1 and 2 addresses are illegal.
Page 378 TC1728 On-Chip System Buses and Bus Bridges Bus Cycle Request/ Address Data Data Data Data Transfer 1 Grant Cycle Cycle Cycle Cycle Cycle Request/ Data Transfer 2 Address Cycle Grant Cycle MCA06110 Figure 4-7 FPI Bus Block Transactions User’s Manual 4-33 V1.0, 2011-12...
Page 379: Fpi Bus Control Unit (Sbcu)
BCU itself will drive the FPI Bus to prevent it from floating electrically. 4.6.1.1 Arbitration on the System Peripheral Bus The TC1728 SPB has three bus agents that can become a SPB bus master (DMA, LFI, PCP). Each agent is supplied an arbitration priority as shown in Table 4-9. DMA controller agent can be assigned to low, medium or high priority by software (via DMA Channel and OCDS control registers).
Page 380 TC1728 On-Chip System Buses and Bus Bridges If there is no request from an SPB bus master, the SPB is granted to a default master (LFI Bridge or PCP) which has been at last the active master. User’s Manual 4-35 V1.0, 2011-12...
Page 381: Starvation Prevention
TC1728 On-Chip System Buses and Bus Bridges 4.6.1.2 Starvation Prevention Starvation prevention is a feature of the SBCU that can take care that even requesting low priority master agents will be granted after a period, where the period length can be controlled by SBCU control registers.
Page 382 Code (ACK) Description NSC: No Special Condition. SPT: Split Transaction (not used in the TC1728). RTY: Retry. Slave can currently not respond to the access. Master needs to repeat the access later. ERR: Bus Error, last data cycle is aborted.
Page 383 TC1728 On-Chip System Buses and Bus Bridges Table 4-11 FPI Bus Operation Codes (OPC) Description 0000 Single Byte Transfer (8-bit) 0001 Single Half-Word Transfer (16-bit) 0010 Single Word Transfer (32-bit) 0100 2-Word Block Transfer 0101 4-Word Block Transfer 0110 8-Word Block Transfer...
Page 384: Bcu Debug Support
TC1728 On-Chip System Buses and Bus Bridges 4.6.3 BCU Debug Support For debugging purposes, the BCU has the capability for breakpoint generation support. This OCDS debug capability is controlled by the Cerberus module and must be enabled by it (indicated by bit SBCU_DBCNTL.EO).
Page 385: Signal Status Triggers
TC1728 On-Chip System Buses and Bus Bridges 4.6.3.2 Signal Status Triggers The signal status debug trigger event conditions are defined by the contents of the SBCU_DBBOS and SBCU_DBCNTL registers. Depending on the selected configuration a wide range of possibilities arise for the creation of a debug trigger event based on FPI Bus status signals.
Page 386: Grant Triggers
TC1728 On-Chip System Buses and Bus Bridges 4.6.3.3 Grant Triggers The signal status debug trigger event conditions are defined via the registers SBCU_DBGRNT and SBCU_DBCNTL. Depending on the configuration of these registers, any combination of FPI Bus master trigger events can be configured. Only the enabled masters in the SBCU_DBGRNT register are of interest for the grant debug trigger event condition.
Page 387: Combination Of Triggers
TC1728 On-Chip System Buses and Bus Bridges 4.6.3.4 Combination of Triggers The combination of the four debug trigger signals to the single BCU breakpoint trigger event is defined via the bits CONCOM[2:0] of register SBCU_DBCNTL (see Figure 4-11). The two address triggers are combined to one address trigger that is further combined with signal status and grant trigger signals.
Page 388 TC1728 On-Chip System Buses and Bus Bridges c) ONA1 = 01 means that the equal match condition for debug address 1 register is selected. d) ONG = 1 means that the grant debug trigger is enabled. e) CONCOM[2:0] = 101...
Page 389 TC1728 On-Chip System Buses and Bus Bridges OCDS Debug Example 3 • Task: Generation of a BCU debug trigger event on any access into address area 01FFFFFF to FFFFFFFF by the PCP. For this task the following programming settings for the BCU breakpoint logic must be executed: 1.
Page 390: System Bus Control Unit Registers
TC1728 On-Chip System Buses and Bus Bridges 4.6.4 System Bus Control Unit Registers Figure 4-12 Table 4-13 are showing the address maps with all registers of the System Bus Control Unit (SBCU) module. SBCU Control Registers Overview Control Registers Address/Data...
Page 391 TC1728 On-Chip System Buses and Bus Bridges Table 4-13 Registers Overview - SBCU Control Registers Short Description Offset Access Mode Reset Description Name Addr. Class Read Write SBCU_ SBCU Error Control U, SV SV Page 4-49 ECON Capture Register SBCU_...
Page 392: Sbcu Id Register Description
TC1728 On-Chip System Buses and Bus Bridges 4.6.4.1 SBCU ID Register Description The identification register allows the programmer version-tracking of the module. The table below shows the identification register which is implemented in the SBCU module. SBCU_ID Module Identification Register...
Page 393: Sbcu Control Registers Descriptions
TC1728 On-Chip System Buses and Bus Bridges 4.6.4.2 SBCU Control Registers Descriptions The SBCU Control Register controls the overall operation of the SBCU, including setting the starvation sample period, the bus time-out period, enabling starvation-protection mode, and error handling. SBCU_CON...
Page 394: Sbcu Error Registers Descriptions
TC1728 On-Chip System Buses and Bus Bridges 4.6.4.3 SBCU Error Registers Descriptions The capture of bus error conditions is enabled by setting SBCU_CON.DBG to 1. In case of a bus error, information about the condition will then be stored in the SBCU error capture registers.
Page 395 TC1728 On-Chip System Buses and Bus Bridges Field Bits Type Description ERRCNT [15:0] FPI Bus Error Counter ERRCNT is incremented on every occurrence of an FPI Bus error. ERRCNT is reset to 0000 after the SBCU_ECON register is read. TOUT...
Page 396 The FPI Bus operation codes are defined in Table 4-11. 1) In the TC1728, aborted accesses to a 0 wait state SPB slave may also increment ERRCNT when the slave generates an error acknowledge. Table 4-14 FPI Bus Read/Write Error Indication...
Page 397 TC1728 On-Chip System Buses and Bus Bridges SBCU_EDAT SBCU Error Data Capture Register (028 Reset Value: 0000 0000 FPIDAT Field Bits Type Description FPIDAT [31:0] Captured FPI Bus Address This bit field holds the 32-bit FPI Bus data that has been captured at an FPI Bus error.
Page 398: Sbcu Ocds Registers Descriptions
TC1728 On-Chip System Buses and Bus Bridges 4.6.4.4 SBCU OCDS Registers Descriptions SBCU_DBCNTL SBCU Debug Control Register (030 Reset Value: 0000 7003 ONA2 ONA1 Field Bits Type Description Status of SBCU Debug Support Enable This bit is controlled by the Cerberus and enables the SBCU debug support.
Page 399 TC1728 On-Chip System Buses and Bus Bridges Field Bits Type Description CONCOM0 Grant and Address Trigger Relation The grant phase trigger condition and the address trigger condition (see CONCOM1) are combined with a logical OR for further control The grant phase trigger condition and the...
Page 400 TC1728 On-Chip System Buses and Bus Bridges Field Bits Type Description ONA2 [25:24] Address 2 Trigger Control No address 2 trigger is generated An address 2 trigger event is generated if the FPI Bus address is equal to SBCU_DBADR2 An address 2 trigger event is generated if...
Page 401 TC1728 On-Chip System Buses and Bus Bridges Field Bits Type Description [3:2], Reserved [11:5], Read as 0; should be written with 0. [19:17], [23:22], [27:26] SBCU_DBGRNT Reset Value: 0000 FFFF SBCU Debug Grant Mask Register (034 ONES Field Bits Type Description...
Page 402 TC1728 On-Chip System Buses and Bus Bridges Field Bits Type Description DMAM DMA Grant Trigger Enable, Medium Priority FPI Bus transactions with medium-priority DMA channels as bus master are enabled for grant trigger event generation FPI Bus transactions with medium-priority DMA...
Page 403 TC1728 On-Chip System Buses and Bus Bridges Field Bits Type Description ADR1 [31:0] Debug Trigger Address 1 This register contains the address for the address 1 trigger event generation. SBCU_DBADR2 SBCU Debug Address 2 Register (03C Reset Value: 0000 0000...
Page 404 TC1728 On-Chip System Buses and Bus Bridges Field Bits Type Description [3:0] Opcode for Signal Status Debug Trigger This bit field determines the type (opcode) of an FPI Bus transaction for which a signal status debug trigger event is generated (if enabled by DBCNTL.ONBOS0 = 1).
Page 405 TC1728 On-Chip System Buses and Bus Bridges Field Bits Type Description [7:5], Reserved [11:9], Read as 0; should be written with 0. [31:13] SBCU_DBGNTT SBCU Debug Trapped Master Register (044 Reset Value: 0000 FFFF ONES Field Bits Type Description DMAH...
Page 406 TC1728 On-Chip System Buses and Bus Bridges Field Bits Type Description DMAM High-Priority DMA FPI Bus Master Status This bit indicates whether the DMA with a medium priority request was FPI Bus master when the break trigger event occurred. The medium-priority DMA was not the FPI bus master.
Page 407 TC1728 On-Chip System Buses and Bus Bridges SBCU_DBADRT SBCU Debug Trapped Address Register (048 Reset Value: 0000 0000 FPIADR Field Bits Type Description FPIADR [31:0] FPI Bus Address Status This register contains the FPI Bus address that was captured when the OCDS break trigger event occurred.
Page 408 TC1728 On-Chip System Buses and Bus Bridges Field Bits Type Description FPIOPC [3:0] FPI Bus Opcode Status This bit field indicates the type (opcode) of the FPI Bus transaction captured from the FPI Bus signal lines when the BCU break trigger event occurred.
Page 409 TC1728 On-Chip System Buses and Bus Bridges Field Bits Type Description FPIWR FPI Bus Write Indication Status This bit indicates the write signal status captured from the FPI Bus signal lines when the BCU break trigger event occurred. Single write transfer or write cycle of an atomic...
Page 410 TC1728 On-Chip System Buses and Bus Bridges Field Bits Type Description FPITAG [19:16] rh FPI Bus Master TAG Status This bit field indicates the master TAG captured from the FPI Bus signal lines when the BCU break trigger event occurred (see Table 4-15).
Page 411: Sbcu Service Request Control Register Description
Request Set Bit [9:8], Reserved Read as 0; should be written with 0. [31:16] Note: Further details on interrupt handling and processing are described in the Interrupt Chapter of this TC1728 User’s Manual. User’s Manual 4-66 V1.0, 2011-12 Buses, V1.9...
Page 412: On Chip Bus Master Tag Assignments
TC1728 On-Chip System Buses and Bus Bridges On Chip Bus Master TAG Assignments Each master interface on the FPI Bus and on the LMB Bus is assigned to a 4-bit (FPI Bus) or 3-bit (LMB Bus) identification number, the master TAG number (see Table 4-15).
Page 413: Program Memory Unit (Pmu)
The devices of this family have at least one Program Memory Unit. This is named “PMU0”. The high-end devices can have additional PMUs which are named “PMU1”, … The TC1728 has only the PMU0. The PMU0 contains the following submodules: •...
Page 414 TC1728 Program Memory Unit (PMU) To/From Local Memory Bus LMB Interface PMU0 Slave Overlay RAM Interface Control ROM Control OVRAM Flash Interface Module BROM DFLASH Emulation PFLASH Memory Interface Emulation Memory PMU0_BasicBlockDiag _generic (ED chip only ) Figure 5-1 PMU0 Basic Block Diagram User’s Manual...
Page 415: Bootrom
TC1728 Program Memory Unit (PMU) BootROM The BootROM in PMU0 has a capacity of 16 KB, organized with double-words of 64 bits. The BootROM consists basically of two parts, used for: • startup and boot SW (also called firmware), and •...
Page 416: Overlay Ram And Data Acquisition
TC1728 Program Memory Unit (PMU) Overlay RAM and Data Acquisition The overlay memory OVRAM is provided in the PMU0 especially for redirection of program memory accesses to the OVRAM by using the data overlay function. The data overlay functionality itself is controlled in the DMI module to avoid any performance penalty during the execution of redirection, and to support also external memories.
Page 417: Access Performance
TC1728 Program Memory Unit (PMU) The base address of the virtual OLDA memory range is A/8FE7 0000 (non- cached/cached space), the end address is A/8FE7 7FFF 5.2.3 Access Performance Write accesses to the PMU Overlay Memory OVRAM are performed with two cycles (because of the read-modify-write for ECC generation) for bytes, half-words and words but in one cycle for double-words.
Page 418 TC1728 Program Memory Unit (PMU) Field Bits Type Description POLDAEN Protection Bit for OLDAEN Bit protection: Bit OLDAEN remains unchanged with register OVRCON write OLDAEN can be changed with current write access to register OVRCON This bit enables OLDAEN write during OVRCON write.
Page 419: Emulation Memory Interface
(byte, half-word, word, double-word). CPU- controlled Load-Modify-Store accesses (with LDMST instruction) are not supported. In the TC1728 production device, the EMEM interface is always disabled. A CPU read access from the Emulation Memory region causes a DSE trap and an LMB bus error. If the Emulation Memory region read access is initiated by a SPB master (e.g.
Page 420: Pmu Id Register
TC1728 Program Memory Unit (PMU) PMU ID Register The PMU_ID register is a read-only register, thus write accesses lead to a bus error trap. Read accesses are permitted in Supervisor Mode SV and in User Mode. The PMU_ID register is defined as follows:...
Page 421: Tuning Protection
TC1728 Program Memory Unit (PMU) Tuning Protection The special tuning protection support represents a security function provided additionally to Flash read/write/OTP protection (see Page 5-21 Chapter 5.6.5) and additionally to the Alternate Boot Mode (see BootROM spec). For details on the tuning protection please contact your Infineon representative.
Page 422: Program And Data Flash
This chapter describes the embedded Flash module of the TC1728. 5.6.1 Introduction The embedded Flash module of TC1728 includes 1.5 MB of Flash memory for code or constant data (called Program Flash) and 64 Kbyte of additional Flash memory used for emulation of EEPROM data (called Data Flash).
Page 423 TC1728 Program Memory Unit (PMU) Redundancy Voltage Control Control Control Flash Command Control SFRs State Machine FCS FSRAM Microcode Address Addr Bus Page Write Program Buffers Flash Write Bus 256 byte WR_DATA 128 byte PF-Read ECC Code ECC Block Bank 0...
Page 424 TC1728 Program Memory Unit (PMU) • User controlled configuration blocks (UCB) in configuration sector for keywords and for sector-specific lock bits (one block for every user; up to three users). • Pad supply voltage also used for program and erase (no VPP pin).
Page 425 TC1728 Program Memory Unit (PMU) • Erase time per sector: max. 1.5 sec. (increased for low frequencies). • Endurance = 60000; i.e. 60000 program/erase cycles per sector are allowed, with a retention of min. 5 years • Dedicated DFlash status information.
Page 426: Architectural And Operational Overview
TC1728 Program Memory Unit (PMU) 5.6.2 Architectural and Operational Overview In the following, an overview of the internal structure and of operations is presented. 5.6.2.1 Sector and Page Architecture The Program Flash as well as the Data Flash memory are characterized by their sector architecture and by their page structure.
Page 427: Data Flash And Eeprom Emulation
TC1728 Program Memory Unit (PMU) times before refreshing the 64K sector. In total, also for each logical sector the max. number of erase cycles is 1000. Erase of the 64K physical sector can be performed with one 64K erase operation or with four 16K erase operations.
Page 428 TC1728 Program Memory Unit (PMU) buffer becomes the active EEPROM region. The “old” DFLASH bank can be erased, when the active EEPROM region has been switched to the “new” DFLASH bank. As a result of the continuously changing assignment of the active EEPROM region in a...
Page 429: Operational Overview
TC1728 Program Memory Unit (PMU) 5.6.2.3 Operational Overview In general, the operations of Program Flash and Data Flash are controlled identically. Therefore, in the following, the operational overview is mainly presented only for the Program Flash. When necessary, additional explanations are made for the Data Flash.
Page 430 TC1728 Program Memory Unit (PMU) to protect against inadvertent writes. Some commands which do not directly control Flash array operations are implemented as single cycle commands. All command cycles are write (store) cycles to the Flash. During command cycles, the low order 16 bits of the address bus (A15–A0) define the Flash command address, and...
Page 431 TC1728 Program Memory Unit (PMU) 2. Execute 32 (Data Flash: 16) ‘Load Page’ commands to transfer double-words or execute 64(32) commands to transfer words to the respective page assembly buffer. Mixed transfers of words and double-words are not allowed (error indication). The first double-word is loaded into the page assembly buffer to the location with address zero (starting address of page register).
Page 432 TC1728 Program Memory Unit (PMU) If the Flash bank, which is addressed, is still busy, the command cycle stall the bus system and the sending master. After the last cycle of the command sequence, the device automatically starts and controls the erase procedure. Start of operation is delayed, if another bank is busy with a write operation at that time.
Page 433 TC1728 Program Memory Unit (PMU) written by user code accessed from Program Flash. In Data Flash, also parallel write operations (programming one bank while erasing the other bank) are possible. Register Access Control Register accesses for polling the status register are allowed in any state, also during erase and program operations (but then executed out of other internal or external memory).
Page 434 TC1728 Program Memory Unit (PMU) and sectors that are protected only by user 1. User 1 can change sectors that are protected only by him but not sectors that are protected by user 0 or user 2. As for read protection, also for short-term disablement of sector write protection a password checking feature is provided.
Page 435 TC1728 Program Memory Unit (PMU) sleep state is requested, all active or pending Flash array operations are at first correctly terminated, and only then the power down state is taken. The wakeup from sleep ramps up the voltage generators, before the Flash read mode is activated again.
Page 436: Flash Access Control And Performance
TC1728 Program Memory Unit (PMU) 5.6.2.4 Flash Access Control and Performance The required number of wait states for an initial access to PFlash or DFlash is related to the maximum operating frequency (including PLL jitter). Because the default after reset is a worst case setting sufficient for all frequencies, the access times have to be configured by the user according to the application’s frequency for optimum...
Page 437 TC1728 Program Memory Unit (PMU) Table 5-2 Selection of Wait States in Relation to Operating Frequency for Flash modules with Ta=50 ns (cont’d) Operating Frequency WS for WS for WS for Initial Read Buffer Prefetch Access Hit Access Line Hit ≤...
Page 438: Functional Description
TC1728 Program Memory Unit (PMU) 5.6.3 Functional Description In the following chapters, the detailed Flash functions and the related user interface are described. 5.6.3.1 Address Mapping The total address range of 4 Gbyte (addresses A31–A0) is divided into 16 segments of each 256 Mbyte, which are addressed by A31–A28.
Page 439 TC1728 Program Memory Unit (PMU) Table 5-3 Flash Memory Map and Access Control in PMU0 Range Size Start Address Access Transaction Description ment Control Control Program Flash 8000 0000 Instr. Access 4x64-bit into cached space Mbyte via LMB PMI cache,...
Page 440: Basic Operating Modes
TC1728 Program Memory Unit (PMU) 5.6.3.2 Basic Operating Modes Generally, the Flash module distinguishes two basic operating modes, the standard read mode and the command mode. Additionally to the read mode, the page mode can be activated. Since the Flash array is represented by three autonomous Flash banks, one bank of Program Flash and two banks of Data Flash, the operating modes belong to every Flash bank and can partly be active concurrently.
Page 441 TC1728 Program Memory Unit (PMU) • UCPA: User configuration page address. • SA: Sector address; base address of sector to be erased. • UCBA: User configuration block address; base address of the 1 Kbyte UC block. • UL: User protection level; the command user level is zero (master user) or one.
Page 442 TC1728 Program Memory Unit (PMU) Table 5-4 Command Sequences for Flash Control 1)2) Command Sequence Cycle Cycle Cycle Cycle Cycle Cycle Reset to Read Address .5554 Data ..xxF0 Enter Page Mode Address .5554 Data ..xx5y *)3) Load Page Address .55F0...
Page 443: Functional Command Description
TC1728 Program Memory Unit (PMU) 3) The address “55F0 ” is used for load DW (64-bit) operations and for load word (32-bit) operations with word transfer on even half of 64-bit bus. In case of word transfers, for every second word the address has to be “55F4...
Page 444 TC1728 Program Memory Unit (PMU) With this command, the ‘page mode’ is entered, indicating that the page assembly buffer is enabled to be filled up with Load Page commands, and that a program operation is in preparation. Selection between assembly buffers of Program Flash and Data Flash is performed with the nibble “y”...
Page 445 TC1728 Program Memory Unit (PMU) In case of a completely filled page assembly buffer, an overrun condition is sampled during Load Page operations. In this case, the write data causing the overflow condition are lost. The overflow condition is indicated by the sequence error flag and by an error interrupt (if enabled), but the execution of a following Write Page command is not suppressed (the page mode is not aborted).
Page 446 TC1728 Program Memory Unit (PMU) the first command cycle is acknowledged with a retry request. After start of program operation also the BUSY flag for the addressed bank is set in FSR. The start of program operation can be delayed: •...
Page 447 TC1728 Program Memory Unit (PMU) confirmation code in the respective UC page, the new protection configuration is valid and active after the next reset. If the protection configuration in an UC block has to be re-programmed (not possible for UCB2), at first the user’s protection must be disabled and then its UC block must be erased.
Page 448 TC1728 Program Memory Unit (PMU) The sector erase algorithm includes an erase quality check that identifies incorrect erased bits in the Flash sector. If re-erasing of weak bits or soft re-programming of over- erased bits is unsuccessful, the verify error flag FSR.VER is set (see Chapter 5.6.6.3).
Page 449 TC1728 Program Memory Unit (PMU) If the Erase Phys Sector operation is used to erase a physical 64K sector of Program Flash (including the 16K sectors), this operation is only executed, if none of its 16K sectors is write protected or if protection is disabled (user 0 and/or user 1). If write protection is not disabled, or if one or more of the included 16K sectors are OTP protected, the erase operation is not started, and the protection error flag PROER is set.
Page 450 TC1728 Program Memory Unit (PMU) Disable Sector Write Protection Sector write protection of all protected sectors belonging to the user’s protection level (only in Program Flash) is temporarily disabled. This is a protected command sequence, using two user defined passwords to release this command.
Page 451 TC1728 Program Memory Unit (PMU) now supported in the PMU. The read protection control flags DCF and DDF in FCON register can now be cleared via FCON register access. The read protection (including global write protection) remains disabled until the command Resume Read/Write Protection is executed, or until the next application reset (including HW and SW reset).
Page 452: Sector, Page And Block Addressing
TC1728 Program Memory Unit (PMU) 5.6.3.5 Sector, Page and Block Addressing As all command cycles of command sequences, sector, page and block addressing as required in the command sequences shall be performed in the non-cached address space of Program Flash and Data Flash (for definition of address mapping see Table 5-3).
Page 453 TC1728 Program Memory Unit (PMU) Table 5-5 Addresses and Sizes of Sectors in Program Flash Sector Phys. Sector Sector Addresses SA Sector Range Sector Size Physical Addr. (hex) A21 – A18– A16 – A13 – 16 KB - 0 - 00’0000 –...
Page 454 TC1728 Program Memory Unit (PMU) Table 5-6). The high order address bits A31 – A22 are again defined by the address mapping of Data Flash or Program Flash. Table 5-6 Addresses of Phys Sectors in DFlash and in PFlash Sector...
Page 455: Register Addresses And Access Restrictions
TC1728 Program Memory Unit (PMU) Table 5-7 Addresses and Sizes of Pages (cont’d) Page Page Page Addresses PA Page Range Number Size Physical Addr. A21– A15– A11– A6– (hex) User Configuration Block UCPneve 256 Byte - 0- - 0- - 0 - 00’0x00 –...
Page 456 TC1728 Program Memory Unit (PMU) Table 5-9 Registers Address Spaces of Flash Registers Module Base Address End Address Note FLASH0 F800 1000 F800 23FF Table 5-11 Within the register address table below, the Access Modes “Read” and “Write” indicate access rights and restrictions as well as values, using symbols as follows:...
Page 457 TC1728 Program Memory Unit (PMU) Table 5-11 Addresses of Flash0 Registers (cont’d) Short Description Address Access Mode Reset Name Read Write FLASH0_ Flash Module F800 2008 U, SV BE Class3 Page Identification Register Reset 5-59 – Reserved F800 200C –...
Page 458: Flash Status Definition
TC1728 Program Memory Unit (PMU) 5.6.3.7 Flash Status Definition The Flash Status Register FSR reflects the overall status of the Flash module after Reset and after reception of the different commands. Sector specific protection states are not indicated in the FSR, but in the registers PROCON0, PROCON1 and PROCON2. The status register is a read-only register.
Page 459 TC1728 Program Memory Unit (PMU) Field Bits Type Description D0BUSY Data Flash Bank 0 Busy HW-controlled status flag. DFlash0 ready, not busy; DFlash0 in read mode. DFlash0 busy; DFlash0 not in read mode. Indication of busy state of DFlash bank 0 because of active execution of program or erase operation;...
Page 460 TC1728 Program Memory Unit (PMU) Field Bits Type Description 3)4) ERASE Erase State HW-controlled status flag. There is no erase operation requested or in progress or just finished Erase operation requested (from FIM) or in action or finished. Set with last cycle of Erase command sequence, cleared with Clear Status command (if not busy) or with power-on reset.
Page 461 TC1728 Program Memory Unit (PMU) Field Bits Type Description 1)2)3) SQER Command Sequence Error No sequence error Command state machine operation unsuccessful because of improper address or command sequence. A sequence error is not indicated if the Reset to Read command aborts a command sequence.
Page 462 TC1728 Program Memory Unit (PMU) Field Bits Type Description RPROIN Read Protection Installed No read protection installed Read protection and global write protection (with or without Data Flash) is configured and correctly confirmed in the User Configuration Block 0. Supported only for the master user (user zero).
Page 463 TC1728 Program Memory Unit (PMU) Field Bits Type Description 1)5) WPRODIS0 Sector Write Protection Disabled for User 0 All protected sectors of user 0 are locked if write protection is installed All write-protected sectors of user 0 are temporarily unlocked, if not coincidently locked by user 2 or via read protection.
Page 464 TC1728 Program Memory Unit (PMU) Field Bits Type Description 17,20, Reserved Read zero, no write 27, 29 Note: The footnote numbers of FSR bits describe the specific reset conditions: 1)Cleared with application reset (class 3 reset) 2)Cleared with command “Reset to Read”...
Page 465: Flash Configuration Control
TC1728 Program Memory Unit (PMU) 5.6.3.8 Flash Configuration Control The Flash Configuration Register FCON reflects and controls the following general Flash configuration functions: • Number of wait states for Flash accesses (see also Table 5-1 for selection). • Indication of installed and active read protection.
Page 466 TC1728 Program Memory Unit (PMU) Field Bits Type Description WSPFLASH [3:0] Wait States for read access to PFlash This bitfield defines the number of wait states, which are used for an initial read access to the Program Flash memory area (see Table 5-1 for selection).
Page 467 TC1728 Program Memory Unit (PMU) Field Bits Type Description WSECDF Wait State for Error Correction of DFlash No additional wait state for error correction One additional wait state for error correction during read access to Data Flash IDLE Dynamic Flash Idle...
Page 468 TC1728 Program Memory Unit (PMU) Field Bits Type Description Disable Code Fetch from Flash Memory This bit enables/disables the code fetch from the internal Flash memory area. Once set, this bit can only be cleared when RPA=’0’. This bit is automatically set with reset and is cleared during rampup, if no RP installed, and during startup (BootROM SW) in case of internal start out of Flash.
Page 469 TC1728 Program Memory Unit (PMU) Field Bits Type Description DDFPCP Disable Data Fetch from PCP Controller This bit enables/disables the data read access to PFlash&DFlash memory via the LFI bridge (used from PCP controller). Once set, this bit can only be cleared when RPA=’0’.
Page 470 TC1728 Program Memory Unit (PMU) Field Bits Type Description EOBM End of Busy Interrupt Mask Interrupt not enabled EOB interrupt is enabled [7:5], Reserved Read/write zero [23:22] Note: The default numbers of wait states represent the slow cases. This is a general proceeding and additionally opens the possibility to execute higher frequencies without changing the configuration.
Page 471: Flash Identification Register
This bit field is C0 . It defines the module as a 32-bit module. MOD_NUMBER [31:16] r Module Number Value This bit field defines a module identification number. For the TC1728 Flash0 this number is 0097 User’s Manual 5-59 V1.0, 2011-12 PMU, V1.47...
Page 472: Error Correction And Margin Control
TC1728 Program Memory Unit (PMU) 5.6.4 Error Correction and Margin Control Error detection and correction is provided for all read accesses to Program Flash and Data Flash. The combination of error detection with the also available margin check provides an excellent verify function for Flash data safety.
Page 473: Margin Check Control
TC1728 Program Memory Unit (PMU) After an erase operation, a correct ECC code (all zero) is provided for the erased sector in the Program Flash as well as in the Data Flash. For details about handling ECC errors and other flags see Chapter 5.6.6.3.
Page 474 TC1728 Program Memory Unit (PMU) MARP Margin Control Register PFLASH (1018 Reset Value: 0000 8000 MARGIN MARGIN Field Bits Type Description MARGIN0 [1:0] PFLASH Margin Selection for Low Level Standard (default) margin High margin for 0 (low) level Reserved Reserved...
Page 475 TC1728 Program Memory Unit (PMU) MARD Margin Control Register DFLASH (101C Reset Value: 0000 8000 MARGIN MARGIN Field Bits Type Description MARGIN0 [1:0] DFLASH Margin Selection for Low Level Standard (default) margin High margin for 0 (low) level Reserved Reserved...
Page 476: Read And Write Protection
TC1728 Program Memory Unit (PMU) 5.6.5 Read and Write Protection For an overview please refer to Chapter 5.6.2.3 In general, three user levels are supported for installation of protection configuration, and three different types of protection can be assigned to the user levels as follows: 1.
Page 477 TC1728 Program Memory Unit (PMU) (e.g. start from external memory or from internal scratchpad memory after bootstrap execution). • If read protection is active and a bootstrap loader is selected by reset configuration, the execution of bootstrap loader is not suppressed because the Flash is fully protected with DCF and DDF (see above).
Page 478 TC1728 Program Memory Unit (PMU) special 32-bit confirmation (lock-) code is written into the UCB0-page2. Only this confirmation code enables the protection and thus the keywords. The confirmation write operation to the second wordline of the User Configuration Block shall be executed only after check of keyword-correctness (with command “Disable Read Protection”...
Page 479: Write And Otp Protection
TC1728 Program Memory Unit (PMU) Read protection can be combined with sector specific write protection. In this case, after execution of the command ‘Disable Read Protection’ only those sectors are unlocked for write accesses, which are not separately write protected.
Page 480: Protection Configuration Indication
TC1728 Program Memory Unit (PMU) The structure and layout of the three UC blocks is shown in Chapter 5.6.5.4 below, the command “Write User Configuration Page” is described in Chapter 5.6.3.4. With the command sequence “Disable Sector Write Protection” a short-term disablement of write protection for user 0 or user 1 is provided.
Page 481 TC1728 Program Memory Unit (PMU) The Flash Protection Configuration registers PROCONx are loaded by the FIM state machine out of the user’s configuration block directly after reset during rampup. The three PROCONx registers are read-only registers. They are defined as follows:...
Page 482 TC1728 Program Memory Unit (PMU) Field Bits Type Description S12/S13L Sectors 12 and 13 Locked for Write Protection by User 0 This bit is only used if PFLASH has more than 1 Mbyte. It indicates whether PFLASH sectors 12+13 (together 512 KB) are write-protected by user 0 or not.
Page 483 TC1728 Program Memory Unit (PMU) PROCON1 Flash Protection Configuration Register User 1 (1024 Reset Value: 0000 0000 S12/ S10/ S9L S8L S7L S6L S5L S4L S3L S2L S1L S0L S13L S11L Field Bits Type Description SnL (n=0-9) Sector n Locked for Write Protection by User 1 These bits indicate whether PFLASH sector n is write-protected by user 1 or not.
Page 484 TC1728 Program Memory Unit (PMU) Field Bits Type Description SPREC SPREC Soft-Programming Recover. Program 1-data. Soft Recover. Page 5-91. 13, 12 Reserved; deliver the corresponding UCB1 entry. Shall be configured to 0. [31:17], Reserved; always read as 0. 15, 14...
Page 485 TC1728 Program Memory Unit (PMU) Field Bits Type Description S10/S11ROM Sectors 10 and 11 Locked Forever by User 2 This bit is only used if PFLASH has more than 0.5 Mbyte. It indicates whether PFLASH sectors 10+11 (together 512 KB) are read-only sectors or not.
Page 486: User Configuration Blocks And
TC1728 Program Memory Unit (PMU) 5.6.5.4 User Configuration Blocks and Pages In the User Configuration Pages, the installation of read and write protection is configured and confirmed by the user. Three UC blocks of each 1 Kbyte are provided for three different users.
Page 487 TC1728 Program Memory Unit (PMU) Aborted Logical Sector Erase (“ALSE”)” on Page 5-91. These bits are not reflected in the PROCON1 register, therefore their correct content can’t be verified. • The keywords are the keywords from user 1 User Configuration Block UCB2 •...
Page 488: Interrupt, Error And Operation Control
TC1728 Program Memory Unit (PMU) 5.6.6 Interrupt, Error and Operation Control Access and/or operational errors (e.g. wrong command sequences) may be reported to the user by interrupts, and they are indicated by flags in the Flash Status Register FSR. Additionally, bus errors may be generated resulting in CPU traps (also shortly called bus error traps, although this is not correct).
Page 489: Handling Errors During Operation
TC1728 Program Memory Unit (PMU) • Not correctable double-bit error of 64-bit read data from PFlash or DFlash (if not disabled for margin check) • Not allowed write access to read only register (see Table 5-11) • Not allowed write access to ENDINIT protected register (see...
Page 490 TC1728 Program Memory Unit (PMU) • Byte transfer to password or data. • “Clear Status” or “Reset to Read” while busy • “Erase Sector” command to DFlash. • Erase UCB with wrong UCBA. New state: Read mode is entered with following exceptions: •...
Page 491 TC1728 Program Memory Unit (PMU) and the sector can not be erased (e.g. in Flash EEPROM emulation) the wordline could be invalidated if needed by marking it with all-one data and the data could be programmed to another empty wordline.
Page 492 TC1728 Program Memory Unit (PMU) be caused by programming a page whose sector was not erased correctly (e.g. aborted erase due to power failure). Under correct operating conditions a VER after programming will practically not occur. A VER after erasing is not unusual.
Page 493 TC1728 Program Memory Unit (PMU) No state change. Just the bit is set. Proposed handling by software: This flag can be used to analyze the state of the Flash memory. During normal operation it should be ignored. In order to count single-bit errors it must be cleared by “Clear Status”...
Page 494: Handling Errors During Startup
(e.g. by identifying old data by version counters). For the TC1728 this robust EEPROM algorithm is required for the usage of the DFlash. Due to the specificity of each application the appropriate usage and implementation of these measures (together with the more elaborate VER handling) must be chosen according to the context of the application.
Page 495 TC1728 Program Memory Unit (PMU) Warning Level These conditions inform the user software about an internally corrected or past error condition. Logical sector corrected: FSR bits set: VER. The Flash detected that a logical sector erase was apparently aborted by reset or power failure.
Page 496: Application Hints And Guidelines
TC1728 Program Memory Unit (PMU) 5.6.6.5 Application Hints and Guidelines Every command execution is started with the last command cycle of the command sequence, and it is indicated by the busy bit of Program Flash or Data Flash in the status register FSR.
Page 497 TC1728 Program Memory Unit (PMU) program memory, e.g. in the scratchpad SPRAM, or in the other Flash module. But user code, that writes command sequences to the Data Flash, can be located in and executed from the Program Flash in the same Flash module.
Page 498 TC1728 Program Memory Unit (PMU) checkerboard pattern. Always four sequential pages must then be programmed as follows: Page 0 with all ones, page 1 remains erased (all zeros), page 2 remains erased (all zeros), page 3 is programmed with all ones. Identically the next four pages are treated, and so on.
Page 499: Power Supply And Reset
TC1728 Program Memory Unit (PMU) 5.6.7 Power Supply and Reset The following chapters describe the required power supplies, the power consumption and its possible reduction, the control of Flash Sleep Mode and the basic control of Reset. 5.6.7.1 Power Supply...
Page 500 TC1728 Program Memory Unit (PMU) Note: The wake-up time is documented in the data sheet. This time may fully delay the interrupt response time in sleep mode. User’s Manual 5-88 V1.0, 2011-12 PMU, V1.47...
Page 501: Reset Control
TC1728 Program Memory Unit (PMU) 5.6.7.4 Reset Control The PMU-part of Flash module (FIM) uses • the application reset (“class 3 reset”), which may include all reset sources (power-on, HW, SW and watchdog reset, if configured), and • the power-on reset.
Page 502 TC1728 Program Memory Unit (PMU) The detection of aborted programming processes can be handled similarly. After programming a block of data an additional page is programmed as marker. When after reset the block of data is readable and the marker is existent it is ensured that the block of data was programmed without interruption.
Page 503 TC1728 Program Memory Unit (PMU) a) If the marker is erased the data part could have been programmed incompletely. Therefore the data part should not be used or alternatively it could be programmed again to a following page. b) If the marker contains incorrect data the data part was most likely programmed correctly but the marker was programmed incompletely.
Page 504 TC1728 Program Memory Unit (PMU) power-on reset (which switches to a slower clock during startup) lets the repair algorithm finish and the device boot successfully again. Attention: The ALSE repair algorithm was designed to recover the device after a reset during erase caused by an accidental loss of power. Any other possible cause of resets must be prevented by the customer.
Page 505: Emergency Programming
Program Memory Unit (PMU) 5.6.8 Emergency Programming This feature allows in the TC1728 to program data to a DFlash bank with minimum latency. This can be used for programming a “crash record” to a pre-erased DFlash area for Airbag applications.
Page 506 TC1728 Program Memory Unit (PMU) page programming time is minimized. Skipping repetition pulses has as consequence a reduced minimum retention and higher PPM rate. When one DFlash bank is busy with an erase process when a page programming in emergency mode is started the normal erase suspend delay is incurred. But in contrast to normal mode programming the erase jobs is silently aborted and not automatically resumed.
Page 507 TC1728 Program Memory Unit (PMU) COMM1 FSI Communication 1 (0004 Reset Value: 0000 0000 DATA STATUS Field Bits Type Description STATUS [7:0] Status This field can be only written by the FSI. DATA [15:8] Data This field can be written by software and by the FSI.
Page 508 TC1728 Program Memory Unit (PMU) Field Bits Type Description [31:16] r Reserved; always read as 0. User’s Manual 5-96 V1.0, 2011-12 PMU, V1.47...
Page 509: Data Access Overlay (Ovc)
TC1728 Data Access Overlay (OVC) Data Access Overlay (OVC) The data overlay functionality provides the capability to redirect data accesses by the TriCore to program memory (segments 8 and A ) called “target memory” to a different memory called “overlay memory”.
Page 510 Redirection of Data Accesses to/from Code Memory to Internal OVRAM or to Emulation Memory (or to External Memory) In the TC1728, the target memory (Program Flash, external memory or OLDA range, see Chapter 6.4.1) can be divided into a maximum of sixteen memory blocks for redirection into an overlay memory.
Page 511 TC1728 Data Access Overlay (OVC) Original Data (Target) Address 4 Bits 28 Bits Offset OMASKx 0000 11111 ..111111111 0 0000 Programmable no match match Compare OTARx TBASE 0000 RABRx OBASE 0000 Redirected 13 Bits (8 KB OVRAM) Address OBASE...
Page 512: Online Data Acquisition (Olda) And Its Overlay
TC1728 Data Access Overlay (OVC) n=0-7. The start address of the block can be an integer multiple of the programmed block size (natural page boundary). If the data segment address is A or 8 , the segment offset of the original data address is compared with the target base addresses of all overlay blocks which are enabled in RABRx.
Page 513: Target And Overlay Memories
TC1728 Data Access Overlay (OVC) functionality to the single enable bits in the 16 block control registers (RABRx) provide compatibility to enable-control in TC1766/96. • One common overlay start bit (OVSTRT) to enable all prepared (enabled) overlay configurations by writing all shadow enable bits into the 16 block control registers in parallel (write-only bit);...
Page 514: Emulation Overlay Memory
TC1728 Data Access Overlay (OVC) zero. During address translation, the upper 19 address bits are set to A/8FE8 using the same segment address as the original data (target) address. For internal overlay, the size of the overlay blocks can be 2 x 16 B, with n = 0 to 7 (16 byte to 2 Kbyte).
Page 515: Block Priority And Access Performance
TC1728 Data Access Overlay (OVC) Note: The Overlay Control does not prevent configuring the translation logic incorrectly so that memory accesses are translated to not implemented or forbidden memory ranges. Block Priority and Access Performance If concurrent matches in more than one enabled overlay block occur, the block with the lowest order number will win and perform the address translation.
Page 516 TC1728 Data Access Overlay (OVC) Table 6-2 Registers Overview Register Register Long Name Offset Access Descript- Short Address Mode ion see Name Read Write OTARx Overlay Target Address Register x 0024 U, SV SV Page 6-9 x ∗ C (x = 0-15)
Page 517 TSEG [31:28] rw Target Segment (reserved) This bit field is reserved for future use, to select a segment. In TC1728 implementation, any access to segments 8 , or A will be checked for a valid base address; return 0 if read; should be written with 0.
Page 518 TSEG [31:28] rw Target Segment (reserved) This bit field is reserved for future use, to select a segment. In TC1728 implementation, any access to segments 8 , or A will be checked for a valid base address; return 0 if read; should be written with 0.
Page 519 TC1728 Data Access Overlay (OVC) If RABRx.IEMS=0, the RABRx register is defined as follows. RABRx (x=0-15) Redirected Address Base Register x +x*C Reset Value: 0FE8 0000 IEMS RC1 RC0 FIXVAL OBASE Field Bits Type Description OBASE [12:4] Overlay Block Base Address This bit field holds the base address of the overlay memory block in the overlay memory OVRAM.
Page 520 TC1728 Data Access Overlay (OVC) Field Bits Type Description OVEN Overlay Enabled This bit controls whether or not the overlay function of overlay block x is enabled. Overlay function of block x is disabled. Overlay function of block x is enabled.
Page 521 TC1728 Data Access Overlay (OVC) If RABRx.IEMS=1 and RABRx.EXOMS=0, the RABRx register is defined as follows. The reset value is meaningless in this case because after reset the register has always the layout defined on Page 6-11. RABRx (x=0-15) Redirected Address Base Register x...
Page 522 TC1728 Data Access Overlay (OVC) Field Bits Type Description IEMS Internal or Emulation/External Memory Select IEMS selects the type of the overlay memory and the size-range of overlay blocks. Internal OVRAM is selected as overlay memory. Block sizes are 2 Bytes, n = 4-11.
Page 523 TC1728 Data Access Overlay (OVC) If RABRx.IEMS=1 and RABRx.EXOMS=1, the RABRx register is defined as follows. The reset value is meaningless in this case because after reset the register has always the layout defined on Page 6-11. RABRx (x=0-15) Redirected Address Base Register x...
Page 524 TC1728 Data Access Overlay (OVC) Field Bits Type Description IEMS Internal or Emulation/External Memory Select IEMS selects the type of the overlay memory and the size-range of overlay blocks. Internal OVRAM is selected as overlay memory. Block sizes are 2 Bytes, n = 4-11.
Page 525 TC1728 Data Access Overlay (OVC) Field Bits Type Description OMASK [10:4] Overlay Address Mask This bitfield determines the overlay block size in OVRAM and the bits used for address comparison and translation. Selectable overlay memory block sizes in OVRAM: 0000000...
Page 526 TC1728 Data Access Overlay (OVC) OMASKx (x=0-15) Overlay Mask Register x +x*C Reset Value: 0FFF FC00 OMASK Field Bits Type Description OMASK [16:10] rw Overlay Address Mask This bitfield determines the overlay block size in EMEM or in external memory (if EXOMS=1) and the bits used for address comparison and translation.
Page 527 TC1728 Data Access Overlay (OVC) Field Bits Type Description [27:17] r Fixed “1” Values Corresponding address bits are participating in the address comparison. Corresponding final address bits are taken from RABR. [9:0], Fixed “0” Values [31:28] Corresponding address bits are not used in the address comparison.
Page 528 TC1728 Data Access Overlay (OVC) The Overlay Control Register OCON is defined as follows: OCON Overlay Control Register (00E0 Reset Value: 0000 0000 SHOVENx Field Bits Type Description SHOVENx Shadow Overlay Enable x (x=0-15) Overlay block x is disabled with next OVSTRT...
Page 529 TC1728 Data Access Overlay (OVC) Field Bits Type Description DCINVAL Data Cache Invalidate No function in devices without without data cache in Tricore. No action Data Cache Lines in DMI are invalidated (flushed). Note: Per write modified cache lines are not invalidated.
Page 530: Bootrom Content
The SSW also calls - in case - other firmware modules. 7.1.1 Boot Options Summary This chapter summarizes the TC1728 startup configurations in user (not test) mode. Internal Start In this basic startup mode, the first user instruction is fetched from the Internal Program Flash of the device.
Page 531: Conditions Upon Ssw Entry
Headers. The checks are performed according to two Headers defined inside the Internal Flash memory of the device. Several Alternate Boot Modes (ABM) are available in TC1728, the differences are in: • which communication channel is used for code downloading upon an error in check- condition: ASC or CAN.
Page 532: Startup Software Main Flow
ERROR ! Prepare Internal Start processing Alternate Boot Mode Final Chip Configuration including Debug System setup & HARR Exiting the SSW Jump to User Code Firmware END AF-firm67-basic_flow-v1.5.vsd Figure 7-1 TC1728 Firmware: SSW main flow User’s Manual V1.0, 2011-12 BOOT_TC1728_TS, V1.1...
Page 533: Entering The Startup Software
SCU_SWRSTCON.SWRSTREQ - if at the same time Software Boot Configuration is selected - SCU_SWRSTCON.SWBOOT=1. Due to the way HWCFG-bit field is handled by TC1728 hardware, at this point of its flow the SSW does not need to do some special processing regarding the startup configuration.
Page 534: Flash Rampup
7.1.3.4 Basic Device Settings The target of this functional module is to initialize several TC1728-registers with the values, which will be first seen by the user - or generally available - after exiting the SSW. Following device resources are initialized here: •...
Page 535: Select And Prepare Startup Modes
- like Bootstrap Loaders and Alternate Boot. Internal Start This is the basic TC1728 type of operation in which the user code is started out of the Internal Flash Memory. The User Start Address STADD is set to the beginning of Internal Flash Memory Module at address A000’0000...
Page 536 STADD := D400'0000 STADD := STADABMx stm_end AF-Exec_Mode_67-ts-v1.3a.vsd Figure 7-2 TC1728 Firmware: Select and Prepare Start Mode Bootstrap Loader Modes The selected Bootstrap Loader (these routines are described in Chapter 10.2) is executed only if the SSW-flag “Reset Configuration Updated” is set (refer to Chapter 10.1.3.2).
Page 537: Final Chip Settings
After downloading (in case) the code, the User Start Address STADD is set to the beginning of PMI Scratchpad RAM at D400’0000 Alternate Boot Modes There are variety of such modes in TC1728, whereas the differences are in: 1. which Bootloader to execute upon an error in ABM Header a) ASC Bootloader...
Page 538 TC1728 BootROM Content b) if Read Protection is Activated (FCON.RPA=1): - SSW enables Code Fetch from Flash; - SSW enables Data Fetch from Flash in general as well as in particular for DMA (FCON.DDFDMA=0) and PCP; - SSW disables Data Fetch from Flash for the Debug Controller.
Page 539: Ending The Ssw And Starting The User Code
ABM Headers. In any Alternate Boot Mode of TC1728 two such Headers are defined - Header 0 and Header 1 (referred as ABM.HD0 and ABM.HD1), respectively user code can be started from up to two different start addresses.
Page 540 = x +x+1 (7.1) This calculation is performed by the SSW using the Memory Checker Module in TC1728. The complete check-procedure for a Header consists of the following steps: 1. check the ABM Header ID at offsets 04 ..07...
Page 541: Startup Errors Handling
Respectively, a second WDT reset will occur being already a locked reset, which can be aborted only by a next power-on sequence. Table 7-3 Errors reported by the TC1728 SSW Coding in Description d12/COMDATA...
Page 542: Bootstrap Loaders
PMI Scratchpad RAM (an Internal Program memory). The loaded code is started after exiting the BootROM. Two interfaces can be utilized for downloading in TC1728 - ASC and CAN. Besides two separate procedures are supporting any of these interfaces/protocols, they have a common first part.
Page 543: Asc Bootstrap Loader
The ASC Bootloading routine implements the following steps: • RxD/TxD pins configuration is done in accordance to the TC1728 definitions, as well as depending either the routine is invoked upon “ASC Bootloader”-startup mode (ASC-only pins are used) or following an ASC-protocol detection upon “Generic Bootloader”-mode (CAN/ASC-shared pins are used but configured to ASC module)
Page 544 (5555 ) and the baud rate registers of the MultiCAN module are set accordingly. The TC1728 is now ready to receive CAN frames with the baud rate of the external host. Acknowledge Phase In the acknowledge phase, the bootstrap loader waits until it receives the next correctly recognized initialization frame from the external host, and acknowledges this frame by generating a dominant bit in its ACK slot.
Page 545: Influencing The Next Ssw-Execution
TC1728 BootROM Content Influencing the next SSW-execution By writing 1 to SYSCON.SETLUDIS (no protection), the user software will prevent automatic update of SCU_STSTAT.HWCFG upon the next application (class 3) reset. If such setting is active when a Bootstrap Loader mode is configured in STSTAT.HWCFG bitfield, after the next class 3 reset the Bootloader routine will not be...
Page 546: Memory Maps
Memory Maps Memory Maps This chapter gives an overview of the TC1728 memory map, and describes the address locations and access possibilities for the units, memories, and reserved areas as “seen” from the two different on-chip buses’ point of view.
Page 547: What Is New
AudoNG and AudoFuture. Major differences of the TC1728 Memory Map compared to AudoNG: • Address map is adapted to the peripheral set of the products (peripherals where added/removed, number of ports is adapted).
Page 548: How To Read The Address Maps
TC1728 Memory Maps How to Read the Address Maps The bus-specific address maps describe how the different bus master devices react on accesses to on-chip memories and modules, and which address ranges are valid or invalid for the corresponding buses.
Page 549 TC1728 Memory Maps Table 8-1 defines the acronyms and other terms that are used in the address maps (Table 8-2 Table 8-4). Table 8-1 Definition of Acronyms and Terms Term Description …BE Means “Bus error” generation. …BET Means “Bus error & trap” generation.
Page 550: Contents Of The Segments
Contents of the Segments This section summarizes the contents of the segments. Segments 0-7 These segments are reserved segments in the TC1728. Segment 8 From the SPB point of view (PCP), this memory segment allows accesses to all PMU memories (PFLASH, DFLASH, BROM, TROM and OVRAM).
Page 551 TC1728 Memory Maps From the LMB point of view (CPU-PMI, CPU-DMI, DMA including. Cerberus and MLI), this memory segment allows non-cached accesses to the PMI scratch-pad RAM (SPRAM). From the DMA point of view, Move Engine, Cerberus and MLI accesses to this segment are processed by the DMA LMB master interface on the LMB Bus.
Page 552: Address Map Of The Fpi Bus System
TC1728 Memory Maps Address Map of the FPI Bus System This chapter describes the system address map from FPI Bus (SPB) point of view. 8.4.1 Segments 0 to 14 Table 8-2 shows the address map of segments 0 to 14 as it is seen from the SPB bus masters PCP, DMA and OCDS.
Page 553 8FE8 1FFF (OVRAM) 8FE8 2000 – Reserved LMBBE & LMBBE 8FEF FFFF SPBBE 8FF0 0000 384 Kbyte Reserved for TC1728 SPBBE SPBBE 8FF5 FFFF emulation device memory 8FF6 0000 – Reserved SPBBE SPBBE 8FFF BFFF 8FFF C000 16 Kbyte...
Page 554 AFE8 1FFF (OVRAM) AFE8 2000 – Reserved LMBBE & LMBBE AFEF FFFF SPBBE AFF0 0000 384 Kbyte Reserved for TC1728 LMBBE & LMBBE AFF5 FFFF emulation device SPBBE memory AFF6 0000 – Reserved LMBBE & LMBBE AFFF BFFF...
Page 555 TC1728 Memory Maps Table 8-2 SPB Address Map of Segment 0 to 14 (cont’d) Seg- Address Size Description Access Type ment Range Read Write D400 0000 8 Kbyte PMI Scratch-Pad RAM access access D400 1FFF (SPRAM) D400 2000 8 Kbyte...
Page 556 TC1728 Memory Maps Table 8-2 SPB Address Map of Segment 0 to 14 (cont’d) Seg- Address Size Description Access Type ment Range Read Write E850 0000 8 Kbyte PMI Scratch-Pad RAM access access E850 1FFF (SPRAM) E850 2000 8 Kbyte...
Page 557: Segment 15
TC1728 Memory Maps 8.4.2 Segment 15 Table 8-3 shows the address map of segment 15 as seen from the SPB bus masters PCP, DMA and OCDS. Please note that access in Table 8-3 means only that an access to an address within the defined address range is not automatically incorrect or ignored.
Page 558 TC1728 Memory Maps Table 8-3 SPB Address Map of Segment 15 (cont’d) Unit Address Size Access Type Range Read Write Port 3 F000 0F00 access access F000 0FFF byte Port 4 F000 1000 access access F000 10FF byte Port 5...
Page 559 TC1728 Memory Maps Table 8-3 SPB Address Map of Segment 15 (cont’d) Unit Address Size Access Type Range Read Write General Purpose Timer 12 1 F000 3500 access access (GPT121) F000 35FF byte Reserved F000 3600 – SPBBE SPBBE F000 37FF...
Page 560 TC1728 Memory Maps Table 8-3 SPB Address Map of Segment 15 (cont’d) Unit Address Size Access Type Range Read Write Reserved F008 0000 – SPBBE SPBBE F00F FFFF Synchronous Serial Interface 3 F010 0000 access access (SSC3) F010 00FF byte...
Page 561 TC1728 Memory Maps Table 8-3 SPB Address Map of Segment 15 (cont’d) Unit Address Size Access Type Range Read Write Reserved F01E 8000 – SPBBE SPBBE F01F FFFF 4 × 64 MLI0 Large Transfer Windows F020 0000 access access F023FFFF...
Page 562 TC1728 Memory Maps Table 8-3 SPB Address Map of Segment 15 (cont’d) Unit Address Size Access Type Range Read Write CPU Slave Interface F7E0 FF00 access access Registers (CPS) F7E0 FFFF byte CPU Core SFRs & GPRs F7E1 0000 access...
Page 563 TC1728 Memory Maps Table 8-3 SPB Address Map of Segment 15 (cont’d) Unit Address Size Access Type Range Read Write LFI Bridge F87F FF00 access access F87F FFFF byte Reserved F880 0000 – LMBBE & LMBBE FFFF FFFF SPBBE User’s Manual 8-18 V1.0, 2011-12...
Page 564: Address Map Of The Local Memory Bus (Lmb)
8FE8 0000 8 Kbyte Overlay memory access access 8FE8 1FFF (OVRAM) 8FE8 2000 – Reserved LMBBET LMBBET 8FEF FFFF 8FF0 0000 384 Kbyte Reserved for TC1728 LMBBET LMBBET 8FF5 FFFF emulation device memory User’s Manual 8-19 V1.0, 2011-12 MemMaps, V1.91...
Page 565 AFE8 0000 8 Kbyte Overlay memory access access AFE8 1FFF (OVRAM) AFE8 2000 – Reserved LMBBET LMBBET AFEF FFFF AFF0 0000 384 Kbyte Reserved for TC1728 LMBBET LMBBET AFF5 FFFF emulation device memory User’s Manual 8-20 V1.0, 2011-12 MemMaps, V1.91...
Page 566 TC1728 Memory Maps Table 8-4 LMB Address Map (cont’d) Seg- Address Size Description Action ment Range Read Write AFF6 0000 – Reserved LMBBET LMBBET AFFF BFFF AFFF C000 16 Kbyte Boot ROM (BROM) access LMBBET AFFF FFFF B000 0000 Reserved...
Page 567 TC1728 Memory Maps Table 8-4 LMB Address Map (cont’d) Seg- Address Size Description Action ment Range Read Write D400 0000 8 Kbyte PMI Scratch-Pad RAM access access D400 1FFF (SPRAM) D400 2000 8 Kbyte access access D400 3FFF D400 4000...
Page 568 TC1728 Memory Maps Table 8-4 LMB Address Map (cont’d) Seg- Address Size Description Action ment Range Read Write F87F FB00 256 byte Overlay Control Unit access access F87F FBFF (OVC) F87F FC00 256 byte Data Memory Interface access access F87F FCFF...
Page 569: Memory Module Access Restrictions
TC1728 Memory Maps Memory Module Access Restrictions Table 8-5 describes which type of accesses are possible to the different memories in the TC1728. Table 8-5 Possible Memory Accesses Memory Byte Half-word Word Double-word SPRAM LDRAM – – – – –...
Page 570: Side Effects From Modules To Ldram
TC1728 Memory Maps Side Effects from Modules to LDRAM Please note that the LDRAM is also used by Boot routine and can be used by the CPU for system tasks: • the Boot routine copies some devices informations during the startup into the LDRAM (see chapter ´BootROM Content´)
Page 571: General Purpose I/O Ports And Peripheral I/O Lines (Ports)
General Purpose I/O Ports and Peripheral I/O Lines (Ports) General Purpose I/O Ports and Peripheral I/O Lines (Ports) The TC1728 has 133 digital General Purpose Input/Output (GPIO) port lines which are connected to the on-chip peripheral units. Basic Port Operation Figure 9-1 is a general block diagram of a TC1728 GPIO port slice.
Page 572 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Each port line has a number of control and data bits, enabling very flexible usage of the line. Each port pincan be configured for input or output operation. In input mode (default after reset), the output driver is switched off (high-impedance).
Page 573 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) All GPIO lines of the TC1728 that are used by the GPTA module (GPTA0) have an emergency stop logic. This logic makes it possible to individually disconnect GPTA outputs from the driving GPTA module outputs and to put them onto a well defined logic state in an emergency case.
Page 574: Description Scheme For The Port Io Functions
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Description Scheme for the Port IO Functions The following two general building block can be used to describe each GPIO pin: Table 9-1 Port x Input/Output Functions Port Select Connected Signal(s) From / to Module Px.y...
Page 575 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) – ENx - the pins in one port having the same ENx (x=0, 1, 2, ...), are controlled as a group by a dedicated HW_EN signal. – SEN - Single EN - the pin is controlled by its own, dedicated, single HW_EN signal •...
Page 576: Port Register Description
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Port Register Description The individual control and data bits of each GPIO port are implemented in a number of registers. The registers are used to configure and use the port as general-purpose I/O or alternate function input/output.
Page 577 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-3 Registers Address Space (cont’d) Module Base Address End Address Note F000 1100 F000 11FF F000 1200 F000 12FF F000 1400 F000 14FF F000 1500 F000 15FF F000 1600...
Page 578 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-4 Registers Overview (cont’d) Register Register Long Name Offset Access Mode Desc. see Short Name Address Read Write Pn_PDR1 Port n Pad Driver Mode 1 0044 U, SV SV, E...
Page 579 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Register Access Rights and Reset Class Table 9-5 RegistersAccess Rights and Reset Classes Register Short Name Access Rights Reset Class Read Write Pn_OUT U,SV U,SV Class 3 Pn_OMR Pn_IOCR0 Pn_IOCR4...
Page 580: Port Input/Output Control Registers
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.3.1 Port Input/Output Control Registers The port input/output control registers select the digital output and input driver functionality and characteristics of a GPIO port pin. Port direction (input or output), pull- up or pull-down devices for inputs, and push-pull or open-drain functionality for outputs can be selected by the corresponding bit fields PCx (x = 0-15).
Page 581 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Pn_IOCR4 (n=0-3) Port n Input/Output Control Register 4 (F000 0C14 + n*100 Reset Value: 2020 2020 P5_IOCR4 Port 5 Input/Output Control Register 4 Reset Value: 2020 2020 Pn_IOCR4 (n=8-9) Port n Input/Output Control Register 4...
Page 582 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description PC8, [7:4], Port Control for Port n Pin 8 to 11 PC9, [15:12], This bit field determines the Port n line x functionality PC10, [23:20], (x = 8-11) according to the coding table (see...
Page 583 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) The structure with one control bit field for each port pin located in different register bytes offers the possibility to configure the port pin functionality of a single pin with byte- oriented accesses without accessing the other PCx bit fields.
Page 584: Pad Driver Mode Register
Pad Driver Mode Register Overview The pad structure of the TC1728 GPIO lines offers the possibility to select the output driver strength and the slew rate. These two parameters are controlled by the bit fields in the pad driver mode registers Pn_PDR0/1, independently from input/output and pull- up/pull-down control functionality as programmed in the Pn_IOCR register.
Page 585 Medium driver Reserved Weak driver Note: TC1728 Data Sheet describes the DC characteristics of all pad classes. Pad Driver Mode Registers This is the general description of the PDR registers. Each port contains its own specific PDR registers, described additionally at each port, that can contain between one and eight PDx fields for PDR0 and PDR1 registers, respectively.
Page 586 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description [2:0] Pad Driver Mode for Pn.0 [6:4] Pad Driver Mode for Pn.1 [10:8] Pad Driver Mode for Pn.2 [14:12] Pad Driver Mode for Pn.3 [18:16] Pad Driver Mode for Pn.4 [22:20] Pad Driver Mode for Pn.5...
Page 587 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description PD12 [18:16] Pad Driver Mode for Pn.12 PD13 [22:20] Pad Driver Mode for Pn.13 PD14 [26:24] Pad Driver Mode for Pn.14 PD15 [30:28] Pad Driver Mode for Pn.15...
Page 588: Pin Function Decision Control Register
Pin Function Decision Control Register Pin Function Decision Control Register The pad structure of the TC1728 GPIO lines offers the possibility toselect digital input or analog ADC input functionalities at Port 11 and Port 12. For the selection of digital input, the parameters defined for Class S pads must be met.
Page 589: Port Output Register
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.3.4 Port Output Register The port output register determines the value of a GPIO pin when it is selected by Pn_IOCRx as output. Writing a 0 to a Pn_OUT.Px (x = 0-15) bit position delivers a low level at the corresponding output pin.
Page 590: Port Output Modification Register
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.3.5 Port Output Modification Register The port output modification register contains control bits that make it possible to individually set, reset, or toggle the logic state of a single port line by manipulating the output register.
Page 591 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-8 Function of the Bits PRx and PSx Function Bit Pn_OUT.Px is not changed. Bit Pn_OUT.Px is set. Bit Pn_OUT.Px is reset. Bit Pn_OUT.Px is toggled. User’s Manual 9-21 V1.0, 2011-12...
Page 592: Emergency Stop Register
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.3.6 Emergency Stop Register All GPIO lines which are used by the GPTA module (GPTA0) have an emergency stop logic implemented (see Figure 9-1). These GPTA related GPIO lines are: •...
Page 593: Port Input Register
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description Emergency Stop Enable for Port n Pin x (x = 0-15) This bit enables the emergency stop function for GPIO lines used as GPTA outputs. If the emergency...
Page 594 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description Port n Input Bit x (x = 0-15) This bit indicates the level at the input pinPn.x. The input level of Pn.x is 0. The input level of Pn.x is 1.
Page 595: Port 0
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Port 0 This section describes the Port 0 functionality in detail. 9.4.1 Port 0 Configuration Port 0 is a 16-bit bi-directional general-purpose I/O port that can be alternatively used for the GPTA I/O lines, HWCFG, CCU6, MSC0, SCU, ERAY and CAN functions.
Page 596 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-9 Port 0 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P0.2 General-purpose input P0_IN.P2 P0_IOCR0. 0XXX GPTA input SCU input...
Page 597 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-9 Port 0 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P0.6 General-purpose input P0_IN.P6 P0_IOCR4. 0XXX GPTA input SCU input...
Page 598 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-9 Port 0 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P0.9 General-purpose input P0_IN.P9 P0_IOCR8. 0XXX GPTA input ERAY input...
Page 599 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-9 Port 0 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P0.13 I General-purpose input P0_IN.P13 P0_IOCR12. 0XXX PC13 GPTA input...
Page 600: Port 0 Registers
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.4.3 Port 0 Registers The following registers are available on Port 0: Table 9-10 Port 0 Registers Register Register Long Name Offset Description Short Name Address P0_OUT Port 0 Output Register...
Page 601: Port 1
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Port 1 This section describes the Port 1 functionality in detail. 9.5.1 Port 1 Configuration Port 1 is a 16-bit bi-directional general-purpose I/O port that can be alternatively used for the SCU, OCDS, GPTA I/O lines, CCU6/GPT12, SSC1 and the ADC0 external multiplexers functions.
Page 602: Port 1 Function Table
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.5.2 Port 1 Function Table Table 9-11 summarizes the I/O control selection functions of each Port 1 line. Table 9-11 Port 1 Functions Port Pin Functionality Associated Port I/O Control Select.
Page 603 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-11 Port 1 Functions (cont’d) Port Pin Functionality Associated Port I/O Control Select. Reg./ I/O Line Reg./Bit Value Field P1.3 General-purpose input P1_IN.P3 P1_IOCR0. 0XXX GPTA input IN19 General-purpose output P1_OUT.P3...
Page 604 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-11 Port 1 Functions (cont’d) Port Pin Functionality Associated Port I/O Control Select. Reg./ I/O Line Reg./Bit Value Field P1.7 General-purpose input P1_IN.P7 P1_IOCR4. 0XXX GPTA input IN23 General-purpose output P1_OUT.P7...
Page 605 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-11 Port 1 Functions (cont’d) Port Pin Functionality Associated Port I/O Control Select. Reg./ I/O Line Reg./Bit Value Field P1.9 General-purpose input P1_IN.P9 P1_IOCR8. 0XXX GPTA input IN25 GPTA input...
Page 606 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-11 Port 1 Functions (cont’d) Port Pin Functionality Associated Port I/O Control Select. Reg./ I/O Line Reg./Bit Value Field P1.11 I General-purpose input P1_IN.P11 P1_IOCR8. 0XXX PC11 GPTA input...
Page 607: Port 1 Registers
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-11 Port 1 Functions (cont’d) Port Pin Functionality Associated Port I/O Control Select. Reg./ I/O Line Reg./Bit Value Field P1.15 I General-purpose input P1_IN.P15 P1_IOCR12. 0XXX PC15 OCDS BRKIN General-purpose output P1_OUT.P15...
Page 608: Port 2
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Port 2 This section describes the Port 2 functionality in detail. 9.6.1 Port 2 Configuration Port 2 is a 14-bit bi-directional general-purpose I/O port that can be used either for the SSC0/SSC1, MSC0, MLI0, CCU6/GPT12 or GPTA0 I/O lines.
Page 609 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-13 Port 2 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P2.2 General-purpose input P2_IN.P2 P2_IOCR0. 0XXX GPTA input IN34...
Page 610 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-13 Port 2 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P2.5 General-purpose input P2_IN.P5 P2_IOCR4. 0XXX GPTA input IN37...
Page 611 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-13 Port 2 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P2.9 General-purpose input P2_IN.P9 P2_IOCR8. 0XXX General-purpose output P2_OUT.P9...
Page 612 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-13 Port 2 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P2.13 I General-purpose input P2_IN.P13 P2_IOCR1 0XXX 2.PC13 SSC1 input...
Page 613: Port 2 Registers
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.6.3 Port 2 Registers The following registers are available on Port 2: Table 9-14 Port 2 Registers Register Register Long Name Offset Description Short Name Address P2_OUT Port 2 Output Register...
Page 614: Port 2 Input/Output Control Register 12
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.6.3.3 Port 2 Input/Output Control Register 12 The PC14 and PC15 bit fields in register P2_IOCR12 are not connected. P2_IOCR12 Port 2 Input/Output Control Register 12 Reset Value: 2020 2020...
Page 615: Port 2 Pad Driver Mode 1 Register
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.6.3.5 Port 2 Pad Driver Mode 1 Register The basic P2_PDR1 register functionality is described on Page 9-16. P2_PDR1 Port 2 Pad Driver Mode 1 Register Reset Value: 0000 0000...
Page 616 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) can be controlled for the emergency stop function. The P2_ESR bits EN[15:8] are not implemented. They are always read as 0 and should be written with 0. User’s Manual 9-46 V1.0, 2011-12...
Page 617: Port 3
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Port 3 This section describes the Port 3 functionality in detail. 9.7.1 Port 3 Configuration Port 3 is a 16-bit bi-directional general-purpose I/O port that can be used for the GPTA0 I/O lines, ASC0/ASC1, SCU, SSC0/SSC1, MultiCAN, MSC0 functions.
Page 618 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-15 Port 3 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P3.2 General-purpose input P3_IN.P2 P3_IOCR0. 0XXX SSC0 input (Slave Mode)
Page 619 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-15 Port 3 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P3.6 General-purpose input P3_IN.P6 P3_IOCR4. 0XXX General-purpose output P3_OUT.P6...
Page 620 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-15 Port 3 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P3.10 I General-purpose input P3_IN.P10 P3_IOCR8. 0XXX PC10 SCU input...
Page 621 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-15 Port 3 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P3.14 I General-purpose input P3_IN.P14 P3_IOCR12. 0XXX PC14 CAN node 1 receive input 0 RXDCAN1...
Page 622: Port 3 Registers
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.7.3 Port 3 Registers The following registers are available on Port 3: Table 9-16 Port 3 Registers Register Register Long Name Offset Description Short Name Address P3_OUT Port 3 Output Register...
Page 623: Port 4
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Port 4 This section describes the Port 4 functionality in detail. 9.8.1 Port 4 Configuration Port 4 is a 4-bit bi-directional general-purpose I/O port that can be used for the GPTA0 I/O lines, MultiCAN, CCU6/GPT12 and SCU functions.
Page 624: Port 4 Registers
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-17 Port 4 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Field Value P4.2 General-purpose input P4_IN.P2 P4_IOCR0.PC2 0XXX GPTA input IN30...
Page 625: Port 4 Output Register
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-18 Port 4 Registers (cont’d) Register Register Long Name Offset Description Short Name Address P4_IOCR0 Port 4 Input/Output Control Register 0 0010 Page 9-10 P4_IN Port 4 Input Register...
Page 626: Port 4 Pad Driver Mode 0 Register
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.8.3.5 Port 4 Pad Driver Mode 0 Register The basic P4_PDR0 register functionality is described on Page 9-15. However, port lines P4.[15:4] are not connected. P4_PDR0 Port 4 Pad Driver Mode 0 Register...
Page 627: Port 5
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Port 5 9.9.1 Port 5 Configuration Port 5 is a 16-bit bi-directional general-purpose I/O port which can be used for the CCU6/GPT12, GPTA I/O lines, SSC0/SSC2, SCU, ERAY, MultiCAN and ADC1 external multiplexers functions.
Page 628 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-19 Port 5 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P5.2 General-purpose input P5_IN.P2 P5_IOCR0. 0XXX GPTA input IN42 General-purpose output P5_OUT.P2...
Page 629 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-19 Port 5 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P5.6 General-purpose input P5_IN.P6 P5_IOCR4. 0XXX GPTA input IN46...
Page 630 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-19 Port 5 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P5.10 I General-purpose input P5_IN.P10 P5_IOCR8. 0XXX PC10 General-purpose output P5_OUT.P10...
Page 631 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-19 Port 5 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P5.14 I General-purpose input P5_IN.P14 P5_IOCR12 0XXX .PC14 ERAY input...
Page 632: Port 5 Registers
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.9.3 Port 5 Registers The following registers are available on Port 5: Table 9-20 Port 5 Registers Register Register Long Name Offset Description Short Name Address P5_OUT Port 5 Output Register...
Page 633: Port 6
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.10 Port 6 Port 6 is an 4-bit GPIO port. Pins associated to it be used in two ways: • as a CMOS Port where each pin outputs one signal, as any other port (only exception - no open drain mode available), and •...
Page 634: Port 6 Function Table
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.10.2 Port 6 Function Table Table 9-21 summarizes the I/O control selection functions of each Port 6 line. Table 9-21 Port 6 Functions Port I/O Pin Functionality Associated Reg./ Port I/O Control Select.
Page 635: Port 6 Registers
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.10.3 Port 6 Registers The following registers are available on Port 6: Table 9-22 Port 6 Registers Register Register Long Name Offset Description Short Name Address P6_OUT Port 6 Output Register...
Page 636: Port 6 Pad Driver Mode 0 Register
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.10.3.4 Port 6 Pad Driver Mode 0 Register The basic P6_PDR0 register functionality is described on Page 9-15. However, port lines P6.[15:4] are not available. P6_PDR0 Port 6 Pad Driver Mode 0 Register...
Page 637: Port 6 Emergency Stop Register
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.10.3.5 Port 6 Emergency Stop Register The basic P6_ESR register functionality is described on Page 9-22. At Port 6, port lines P6.[3:0] have GPTA outputs. Therefore, the P6_ESR bits EN[15:4] are not implemented.
Page 638: Port 8
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.11 Port 8 This section describes the Port 8 functionality in detail. 9.11.1 Port 8 Configuration Port 8 is an 14-bit bi-directional general-purpose I/O port which can be used for CCU6/GPT12, SSC3 and the GPTA0 I/O lines.
Page 639: Port 8 Function Table
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.11.2 Port 8 Function Table Table 9-23 summarizes the I/O control selection functions of each Port 8 line. Table 9-23 Port 8 Functions Port Pin Functionality Associated Port I/O Control Select.
Page 640 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-23 Port 8 Functions (cont’d) Port Pin Functionality Associated Port I/O Control Select. Reg./ I/O Line Reg./Bit Value Field P8.2 General-purpose input P8_IN.P2 P8_IOCR0. 0XXX SSC3 input (Master MTSR3...
Page 641 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-23 Port 8 Functions (cont’d) Port Pin Functionality Associated Port I/O Control Select. Reg./ I/O Line Reg./Bit Value Field P8.6 General-purpose input P8_IN.P6 P8_IOCR4. 0XXX General-purpose output P8_OUT.P6 1X00...
Page 642 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-23 Port 8 Functions (cont’d) Port Pin Functionality Associated Port I/O Control Select. Reg./ I/O Line Reg./Bit Value Field P8.11 I General-purpose input P8_IN.P11 P8_IOCR8. 0XXX PC11 General-purpose output P8_OUT.P11...
Page 643: Port 8 Register
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.11.3 Port 8 Register The following registers are available on Port 8: Table 9-24 Port 8 Registers Register Register Long Name Offset Description Short Name Address P8_OUT Port 8 Output Register...
Page 644: Port 8 Input/Output Control Register 12
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.11.3.3 Port 8 Input/Output Control Register 12 PC14 and PC15 bit fields in register P8_IOCR12 are not connected. P8_IOCR12 Port 8 Input/Output Control Register 12 Reset Value: 2020 2020 28 27...
Page 645: Port 8 Pad Driver Mode 1 Register
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.11.3.5 Port 8 Pad Driver Mode 1 Register The basic P8_PDR1 register functionality is described on Page 9-15. P8_PDR1 Port 8 Pad Driver Mode 1 Register Reset Value: 0000 0000...
Page 646: Port 9
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.12 Port 9 This section describes the Port 9 functionality in detail. 9.12.1 Port 9 Configuration Port 9 is a 9-bit bi-directional general-purpose I/O port which can be used for the CCU6 and GPTA0 I/O lines and OCDS/JTAG.
Page 647: Port 9 Function Table
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.12.2 Port 9 Function Table Table 9-25 summarizes the I/O control selection functions of each Port 9 line. Table 9-25 Port 9 Functions Port I/O Pin Functionality Associated Port I/O Control Select.
Page 648 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-25 Port 9 Functions (cont’d) Port I/O Pin Functionality Associated Port I/O Control Select. Reg./ Reg./Bit Field Value I/O Line P9.4 General-purpose input P9_IN.P4 P9_IOCR4.PC4 0XXX CCU61 CC62INC General-purpose output P9_OUT.P4...
Page 649 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-25 Port 9 Functions (cont’d) Port I/O Pin Functionality Associated Port I/O Control Select. Reg./ Reg./Bit Field Value I/O Line P9.7 General-purpose input P9_IN.P7 P9_IOCR4.PC7 0XXX CCU61 CC60INC General-purpose output P9_OUT.P7...
Page 650: Port 9 Registers
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.12.3 Port 9 Registers The following registers are available on Port 9: Table 9-26 Port 9 Registers Register Register Long Name Offset Description Short Name Address P9_OUT Port 9 Output Register...
Page 651: Port 9 Input/Output Control Register 8
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.12.3.3 Port 9 Input/Output Control Register 8 P9_IOCR8 Port 9 Input/Output Control Register 8 Reset Value: 2020 2020 PC11 PC10 Field Bits Type Description [7:4] Port Control for P9.8 This bit field determines the P9.8 functionality.
Page 652: Port 9 Pad Driver Mode 1 Register
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.12.3.5 Port 9 Pad Driver Mode 1 Register The basic P9_PDR1 register functionality is described on Page 9-15. However, port lines P9.[15:9] are not connected. P9_PDR1 Port 9 Pad Driver Mode 1 Register...
Page 653: Port 10
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.13 Port 10 This section describes the Port 10 functionality in detail. 9.13.1 Port 10 Configuration Port 10 is a 4-bit bi-directional general-purpose I/O port which can be used for SSC2 functions.
Page 654 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-27 Port 10 Functions (cont’d) Port Pin Functionality Associated Port I/O Control Select. Reg./ I/O Line Reg./Bit Value Field P10.2 General-purpose input P10_IN.P2 P10_IOCR0. 0XXX SSC2 input SCLK2B General-purpose output P10_OUT.P2...
Page 655: Port 10 Registers
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.13.3 Port 10 Registers The following registers are available on Port 10: Table 9-28 Port 10 Registers Register Register Long Name Offset Description Short Name Address P10_OUT Port 10 Output Register...
Page 656: Port 10 Pad Driver Mode 0 Register
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.13.3.4 Port 10 Pad Driver Mode 0 Register The basic P10_PDR0 register functionality is described on Page 9-15. However, port lines P10.[15:4] are not available. P10_PDR0 Port 10 Pad Driver Mode 0 Register...
Page 657: Port 11
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.14 Port 11 This section describes the Port 11 functionality in detail. 9.14.1 Port 11 Configuration Port 11 is a 16-bit input port. Table 9-29 summarizes the input control selection functions of each Port 11 line.
Page 658: Port 11 Function Table
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.14.2 Port 11 Function Table Table 9-29 summarizes the input control selection functions of each Port 11 line. If digital input functionality is selected, the digital input needs to meet the criteria defined for the Class S pads.
Page 659 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-29 Port 11 Functions (cont’d) Port I/O Pin Functionality Associated Port Functionality Control Reg./ Input Select Line Reg./Bit Field Value P11.12 I ADC Analog Input AN28 P11_PDISC.PDIS12 1 Digital Input DIG12 P11.13 I...
Page 660: Port 11 Registers
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.14.3 Port 11 Registers The following registers are available on Port 11: Table 9-30 Port 11 Registers Register Register Long Name Offset Description Short Name Address P11_IOCR0 Port 11 Input/Output Control Register 0...
Page 661: Port 11 Input/Output Control Registers
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.14.4 Port 11 Input/Output Control Registers P11_IOCR0 Port 11 Input/Output Control Register 0 Reset Value: 2020 2020 28 27 24 23 20 19 16 15 12 11 Field Bits Type Description...
Page 662 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) P11_IOCR4 Port 11 Input/Output Control Register 4 Reset Value: 2020 2020 28 27 24 23 20 19 16 15 12 11 Field Bits Type Description PC4, [7:4], Port Control for Port n Pin x...
Page 663 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) P11_IOCR12 Port 11 Input/Output Control Register 12 Reset Value: 2020 2020 28 27 24 23 20 19 16 15 12 11 PC15 PC14 PC13 PC12 Field Bits Type Description PC12,...
Page 664: Port 11 Pin Function Decision Control Register
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.14.5 Port 11 Pin Function Decision Control Register P11_PDISC Port 11 Pin Function Decision Control Register(60 Reset Value: 0000 FFFF PDIS PDIS PDIS PDIS PDIS PDIS PDIS PDIS PDIS PDIS...
Page 665 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description PDIS4 Pin Function Decision Control for Pin 4 The bit selects the function of P11.4. The default state of the pad selects the ADC analog input.
Page 666 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description PDIS11 Pin Function Decision Control for Pin 11 The bit selects the function of P11.11. The default state of the pad selects the ADC analog input.
Page 667: Port 12
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.15 Port 12 This section describes the Port 12 functionality in detail. 9.15.1 Port 12 Configuration Port 12 is a 4-bit input port. Table 9-32 summarizes the input control selection functions of each Port 12 line.
Page 668: Port 12 Function Table
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.15.2 Port 12 Function Table Table 9-32 summarizes the input control selection functions of each Port 12 line. If digital input functionality is selected, the digital input needs to meet the criteria defined for the Class S pads.
Page 669: Port 12 Registers
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.15.3 Port 12 Registers The following registers are available on Port 12: Table 9-33 Port 12 Registers Register Register Long Name Offset Description Short Name Address P12_IOCR0 Port 12 Input/Output Control Register 0...
Page 670: Port 12 Input/Output Control Registers
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.15.4 Port 12 Input/Output Control Registers P12_IOCR0 Port 12 Input/Output Control Register 0 Reset Value: 2020 2020 28 27 24 23 20 19 16 15 12 11 Field Bits Type Description...
Page 671: Port 12 Pin Function Decision Control Register
TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.15.5 Port 12 Pin Function Decision Control Register P12_PDISC Port 12 Pin Function Decision Control Register(60 Reset Value: 0000 000F PDIS PDIS PDIS PDIS Field Bits Type Description PDIS0 Pin Function Decision Control for Pin 0 The bit selects the function of P12.0.
Page 672 TC1728 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description [31:16] r Reserved Read as 0; should be written with 0. User’s Manual 9-102 V1.0, 2011-12 Ports, V2.0...
Page 673: Peripheral Control Processor (Pcp)
Peripheral Control Processor (PCP) This chapter describes the Peripheral Control Processor (PCP), its architecture, programming model, registers, and instructions. The TC1728’s PCP is an enhanced version of the TC1767’s and TC1797’s PCP peripheral control processor, which is an enhanced version of the TC1766’s and TC1796’s PCP, which is again an enhanced version of the TC1775 PCP.
Page 674: Switchable Core Clock Ratio
10.2 Peripheral Control Processor Overview The PCP in the TC1728 performs tasks that would normally be performed by the combination of a DMA controller and its supporting CPU interrupt service routines in a traditional computer system. It could easily be considered as the host processor’s first line of defence as an interrupt-handling engine.
Page 675: Pcp Architecture
TC1728 Peripheral Control Processor (PCP) 10.3 PCP Architecture The PCP is made up of several modular blocks as follows. Please refer to Figure • PCP Processor Core • Code Memory (CMEM) • Parameter Memory (PRAM) • PCP Interrupt Control Unit (PICU) •...
Page 676: Pcp Processor
TC1728 Peripheral Control Processor (PCP) 10.3.1 PCP Processor The PCP Processor is the main engine of the PCP. It contains an instruction pipeline, a set of GPRs, an arithmetic/logic unit (ALU), as well as control and status registers and logic. Its instruction set is optimized especially for the tasks it has to perform.
Page 677: Pcp Code Memory
Page 159 for the implemented type and size of the code memory in the TC1728. The PCP CMEM is viewed from the FPI Bus as a 32-bit wide memory, that must be accessed with 32-bit (word) accesses, and is addressed with byte addresses. Thus, care has to be taken when calculating PCP instruction FPI addresses.
Page 678: Pram Protection
TC1728 Peripheral Control Processor (PCP) concatenated with a 6-bit offset, is provided for arbitrary access to the PRAM. The effective address is a 14-bit word address, allowing a PRAM size of up to 64 Kbytes. The actual type (SRAM, DRAM, etc.) and size of the parameter RAM is implementation- specific;...
Page 679 TC1728 Peripheral Control Processor (PCP) program when it is suspended in favor of a higher-priority Service Request. Please refer Section 10.6.3 for more detailed information on the operation of these nodes. User’s Manual 10-7 V1.0, 2011-12 PCP, V2.09...
Page 680: Pcp Programming Model
TC1728 Peripheral Control Processor (PCP) 10.4 PCP Programming Model The PCP programming model can be viewed as a set of autonomous programs, or tasks, called channel programs, that share the processing resources of the PCP. Channel programs may be short and simple, or very complex; but they can coexist persistently within the PCP.
Page 681: Register R0
TC1728 Peripheral Control Processor (PCP) R7 is the only one of the eight registers that may not be used as a full GPR. The most significant 16 bits of R7 may not be written, and will always read back as 0. However, no error will occur when writing to the most significant 16 bits.
Page 682: Register R6
TC1728 Peripheral Control Processor (PCP) 10.4.1.4 Register R6 Register R6 may also be used as a general-use register. Again however, there are some instructions that use fields within R6. If the COPY or EXIT instructions are used, then the field R6.CNT1 can optionally be used implicitly as a counter. If an EXIT instruction is used that causes an interrupt, R6.SRPN and R6.TOS must be configured properly prior...
Page 683: Register R7
TC1728 Peripheral Control Processor (PCP) 10.4.1.5 Register R7 Register R7 is an exception with respect to the other registers in that not all bits within the register can be written, and the implicit use of the remaining bits virtually excludes the use of R7 as a GPR.
Page 684 TC1728 Peripheral Control Processor (PCP) PCP Register R7 Reset Value: 0000 0000 DPTR RES CEN IEN CNZ Field Bits Type Description [31:16] r Reserved read as 0; should be written with 0. DPTR [15:8] Data Pointer Segment Address for PRAM...
Page 685: Contexts And Context Models
TC1728 Peripheral Control Processor (PCP) 10.4.2 Contexts and Context Models After initialization, the instruction sequence of a PCP channel program is permanently stored (i.e. usually at least as long as the application is running) in the CMEM, and data parameters are held in the PRAM. These will remain stored regardless of whether a...
Page 686 TC1728 Peripheral Control Processor (PCP) To distinguish the actual register contents from the copies stored in the PRAM context regions, the term CRx is used throughout the rest of this document to refer to the register values in the context regions. Registers R6 and R7 are always handled in a special way...
Page 687 TC1728 Peripheral Control Processor (PCP) Stored Context in PRAM PCP Register Set Restore Full Context 8 Words Save Small Context Restore 4 Words Save Minimum Context Restore 2 Words Save MCA06136 Figure 17 PCP Context Models User’s Manual 10-15 V1.0, 2011-12...
Page 688: Context Save Area
PRAM in the TC1728. As an example, a PRAM of 2 Kbytes, solely used for the CSA, can store up to 255 Minimum Contexts, allowing the highest SRPN used for a PCP service request to be 255 (remember, an SRPN of 0 and an associated context region is never used;...
Page 689 TC1728 Peripheral Control Processor (PCP) If portions of the PRAM are used for other variables and global data, the space available for the CSA and the range of valid SRPNs is reduced by the memory space required for this data. For best utilization of PRAM, it is advisable to have the CSA grow upwards as a contiguous area without any “holes”, meaning that all SRPNs in the range 1 …...
Page 690 TC1728 Peripheral Control Processor (PCP) Full Context Small Context Minimum Context PRAM PRAM PRAM Memory Memory Memory Context SRPN = n1 n1×8 Context SRPN = n2 n2×4 Context SRPN = n3 Context n3×2 SRPN = 2 Context SRPN = 3...
Page 691: Context Restore Operation For Cr6 And Cr7
TC1728 Peripheral Control Processor (PCP) When choosing the Context Model for a given application, the following considerations can be helpful. When choosing the Small or the Minimum Context Models, save and restore operations for registers not handled in the automatic context operations can still be handled through explicit load and store instructions under control of the user.
Page 692 TC1728 Peripheral Control Processor (PCP) Channel Resume Mode Figure 19 illustrates the operation of a context restore for a “new” channel program when Channel Resume Mode has been selected (see Page 28). The PC is loaded from CR7[31:16], and the lower half of R7 is loaded from CR7[15:0]. The operating priority of the channel is taken from CR6[31:24] and all of R6 is loaded from CR6.
Page 693 TC1728 Peripheral Control Processor (PCP) Channel Restart Mode Figure 20 illustrates the operation of a context restore for a “new” channel program when Channel Restart Mode has been selected (see Page 27). The PC is loaded with the channel entry table address, and the lower half of R7 is loaded from CR7[15:0]. The upper half of CR6 is discarded.
Page 694 TC1728 Peripheral Control Processor (PCP) Suspended Channel Restart Figure 21 illustrates the operation of a context restore for a “suspended” channel program. The PC is loaded from CR7[31:16] (regardless of the Channel Start Mode), and the lower half of R7 is loaded from CR7[15:0]. All of R6 is loaded from CR6. The figure also shows how the operating priority of the channel (PCP_IR.CPPN) is restored from...
Page 695: Context Save Operation For Cr6 And Cr7
TC1728 Peripheral Control Processor (PCP) 10.4.2.4 Context Save Operation for CR6 and CR7 The operation of R6 and R7 context save varies according to whether the save operation is the result of a channel exit condition, or whether the channel is being suspended in favor of a higher-priority channel program.
Page 696 TC1728 Peripheral Control Processor (PCP) Channel Restart Mode Figure 23 illustrates the operation of a context save for a channel exit when Channel Restart Mode has been selected. This is the same as for Channel Resume mode except that the PC value is discarded, and the appropriate Channel Entry Table address is written to CR7[31:16].
Page 697 TC1728 Peripheral Control Processor (PCP) Channel Suspend Figure 24 illustrates the operation of a context save for a channel that is being suspended. This is the same as for Channel Resume mode except that an interrupt request is created to allow the channel to be restarted at a later time. This restore...
Page 698: Initialization Of The Contexts
TC1728 Peripheral Control Processor (PCP) 10.4.2.5 Initialization of the Contexts The programmer is responsible for configuring each channel program’s context before commencing operation. Because this must be done by writing to the PCP across the FPI Bus, it is important to understand exactly where each channel program’s context is from...
Page 699: Channel Programs
PCP channels. The individual channel programs for the individual PCP service requests can usually be viewed as independent and separate programs. There is no background program defined and running for the PCP in TC1728 as there would be with traditional processors.
Page 700: Channel Resume Mode
TC1728 Peripheral Control Processor (PCP) It is recommended that all EXIT instructions for all channels should use the EP = 0 setting when the PCP is operated in Channel Restart Mode (see Page 117). Note that when Channel Restart Mode is in use a Channel Entry Table must be provided with a valid entry for every channel being used.
Page 701 TC1728 Peripheral Control Processor (PCP) Channel Restart Mode Channel Resume Mode Code Memory Code Memory CMEM CMEM Channel #2 Main Code Channel #n1 Main Code Channel #2 Main Code Channel #3 Main Code Channel #n1 Channel #1 Main Code Main Code...
Page 702: Pcp Operation
10.5.1 PCP Initialization The PCP is placed in a quiescent state when the TC1728 is first powered-on or reset. Before a channel program can be enabled, the PCP as a whole must be initialized by some other FPI Bus master, typically the CPU. Initialization steps include: •...
Page 703: Channel Exit And Context Save Operation
TC1728 Peripheral Control Processor (PCP) After the channel program starts, the value of R6 may be changed without altering the value of the effective CPPN, because updates to the value of R6.CPPN have no effect until the next invocation of the channel program.
Page 704: Error Condition Channel Exit
TC1728 Peripheral Control Processor (PCP) • If ST = 1 is specified bit R7.CEN (Channel Enable) is cleared (i.e. the channel is disabled). • If EP = 0 is specified or PCP_CS.RCB = 1 (Channel Restart Mode has been selected), the PCP program counter to be saved to context location CR7.PC is set to the appropriate channel entry table address.
Page 705: Debug Exit
TC1728 Peripheral Control Processor (PCP) • The PC of the instruction that was executing when the error occurred is stored in PCP_ES.EPC. • The number of the channel program that was executing when the error occurred is stored in PCP_ES.EPN.
Page 706: Pcp Interrupt Operation
TC1728 Peripheral Control Processor (PCP) Note: The DEBUG instruction must be only used in DEBUG mode; otherwise an “Illegal Operation” (IOP) error will be generated. 10.6 PCP Interrupt Operation The PICU and the PSRNs (PCP_SRC[11:0]) are similar to the CPU’s ICU and all other SRNs in the system.
Page 707: Issuing Service Requests To Cpu Or Pcp
TC1728 Peripheral Control Processor (PCP) 10.6.1 Issuing Service Requests to CPU or PCP The PCP may use one of two mechanisms to raise an interrupt request to the CPU or itself. The first, and most inefficient, method for a PCP channel program is to issue service requests by performing an FPI Bus write operation to an external service request node (SRN).
Page 708: Issuing Pcp Service Requests
(x = 4 to 8) with a TOS value representing a non-available interrupt bus or 11 in the TC1728) will disable Service Request Node x. The actual service request flag and the service request priority number of the PCP_SRCx registers are updated by the PCP when it generates an implicit service request.
Page 709: Service Request On Exit Instruction
TC1728 Peripheral Control Processor (PCP) Further differences between these three mechanisms are detailed in the following sections. 10.6.4.1 Service Request on EXIT Instruction An implicit PCP service request is issued when the INT field of the EXIT instruction is set to 1 and the specified condition code, cc_B, of this instruction is true.
Page 710: Service Request On Error
TC1728 Peripheral Control Processor (PCP) Extended Service Request Node. This allows for the posting of an interrupt request to the PCP on exit from the new channel program. 10.6.4.3 Service Request on Error While a service request triggered through an EXIT instruction is optional and can be issued either to the CPU or to the PCP itself, a service request due to an error condition will always be automatically issued and will always be directed to the CPU.
Page 711: Pram Protection
TC1728 Peripheral Control Processor (PCP) To avoid such a deadlock, the PICU performs a special arbitration round as soon as the PCP queue becomes full. In this arbitration round, only the service request nodes assigned to the PCP queue are allowed to participate; all service requests from nodes external to the PCP are excluded, regardless of whether their priorities are higher or lower than those of the PCP queue.
Page 712 TC1728 Peripheral Control Processor (PCP) Writable by FPI? Region Writable by PCP Software? Open PRAM PPROT.FBASE General Channel PRAM PPROT.PSIZE Yes/No Protected Channel PRAM (can be limited to writes by Protected Channels only) CS.PPS Yes/No Context (can be protected against...
Page 713: Protection Of Pram Against Fpi Writes
TC1728 Peripheral Control Processor (PCP) write access to an area of PRAM that cannot be modified by an Unprotected Channel Program. Determination of whether a channel is Protected or Unprotected is performed by examination of the channel number against a programmable threshold (programmed via PCP_PPROT.PTHRES).
Page 714: Protected Channel Pram Protection
TC1728 Peripheral Control Processor (PCP) Note: This scheme also limits the number of Channel Programs that can be invoked. Note: FPI PRAM write accesses to PRAM are unaffected by this protection. 10.7.2.2 Protected Channel PRAM Protection To ensure that an Unprotected Channel Program cannot corrupt the PRAM assigned to a protected channel program it is necessary to protect the PRAM space used by the protected channels from instruction executed by non-protected channels.
Page 715: Operation As An Fpi Slave
TC1728 Peripheral Control Processor (PCP) This function is controlled by the PCP_FWWIN register (see Page 93). 10.8.2 Operation as an FPI Slave The PCP is visible to FPI Masters as a 256 Kbyte R/W block of memory on the System Bus.
Page 716: Pcp Error Handling
TC1728 Peripheral Control Processor (PCP) 10.9 PCP Error Handling The PCP contains a number of fail-safe mechanisms to ensure that error conditions are handled gracefully and predictably. In addition to providing an extra level of system robustness suitable for high integrity and safety-critical systems, these mechanisms can often ease the task of finding programming errors during the development process.
Page 717: Protected Channel Pram
TC1728 Peripheral Control Processor (PCP) • An incoming interrupt request causes the PCP to attempt to load a context from outside the CSA. This prevents the PCP from running an invalid channel program as a result of an invalid interrupt request.
Page 718: Instruction Address Error
TC1728 Peripheral Control Processor (PCP) Note: The DEBUG instruction must be only used in DEBUG mode otherwise it will be considered to be an illegal operation and will generate an IOP error. 10.9.5 Instruction Address Error An Instruction Address Error is generated if the PCP attempts to execute an instruction from an illegal address.
Page 719: Memory Integrity Error Detection And Correction
TC1728 Peripheral Control Processor (PCP) Data Array Mapping, no error detection/correction No mapping of the ECC bits is performed. Writes to the memory will not affect the ECC bits. Error correction/detection for the memory is disabled. Normal operation (with the exception that ECC protection is not operational) is possible.
Page 720: Definitions
TC1728 Peripheral Control Processor (PCP) Note: Before enabling Error Detection/Correction on an SRAM (i.e. CMEM or PRAM) the user must ensure that all locations within the SRAM have been initialised. If this is not done then unwanted spurious memory errors can be generated.
Page 721 TC1728 Peripheral Control Processor (PCP) Table 24 Memory Integrity Error Modes xSECE xIEE SMACON Description or 10 Array Mapping. All single and double-bit memory integrity errors ignored. or 11 No Memory Integrity Handling. All single and double-bit memory integrity errors ignored.
Page 722: Instruction Set Overview
Peripheral Control Processor (PCP) 10.12 Instruction Set Overview The following sections present an overview of the instruction set and the available addressing modes of the PCP in the TC1728. 10.12.1 DMA Primitives Table 18 describes the two DMA instructions of the PCP.
Page 723: Load And Store
TC1728 Peripheral Control Processor (PCP) 10.12.2 Load and Store Table 19 describes the load and store instructions of the PCP. Note: If a conditional instruction’s condition code is false, the operation will be treated as a “No Operation”. Register values will not be changed and the flags will not be updated.
Page 724: Arithmetic And Logical Instructions
TC1728 Peripheral Control Processor (PCP) 10.12.3 Arithmetic and Logical Instructions Arithmetic instructions that are fully register-based execute conditionally depending on the specified Condition Code A (see Page 101). All other arithmetic instructions such as PRAM (.PI), indirect (.I), and FPI (.F and .IF) execute unconditionally.
Page 725 TC1728 Peripheral Control Processor (PCP) Table 29 Logical Instructions Logical Or Register OR register (conditionally) OR.F Content of FPI Bus address location OR register (byte, half-word or word) OR.PI Content of PRAM address location OR register MSET.PI Set specified bits within a PRAM location...
Page 726: Bit Manipulation
Set carry flag depending on value of specified register bit 10.12.5 Flow Control Table 23 describes flow control instructions of the PCP in the TC1728. Table 31 Flow Control Instructions Jump Jump conditionally to PC + short immediate offset address JC.A...
Page 727: Addressing Modes
TC1728 Peripheral Control Processor (PCP) 10.12.6 Addressing Modes The PCP needs to address locations in memory in different ways, as determined by the type of memory being accessed and the type of action being performed on that location. 10.12.6.1 FPI Bus Addressing All FPI Bus accesses from the PCP are indirect to some extent.
Page 728: Pram Addressing
TC1728 Peripheral Control Processor (PCP) 10.12.6.2 PRAM Addressing The PRAM is always addressed indirectly by the PCP. The normal address used is the value of the R7.DPTR field (8 bits) concatenated with an immediate 6-bit offset value encoded in the instruction, yielding a 14-bit word address. This enables access to 16 Kwords (64 Kbytes).
Page 729 TC1728 Peripheral Control Processor (PCP) • Effective JUMP Address[15:0] = NextPC + Sign-Extend(#offset6); +/- 32 instructions The function NextPC indicates the instruction that would be fetched next by the program counter. Instructions using this addressing are JL, JC and JC.I.
Page 730: Fpi Interface
10.13 FPI Interface Any FPI Bus master (on the TC1728’s System Peripheral Bus) can access the three distinct PCP address ranges from the FPI Bus side, on the other hand the PCP master interface can also access any address on the FPI bus. Normally, the CPU initializes the control registers via FPI Bus access.
Page 731: Access To The Pram From The Fpi Bus
TC1728 Peripheral Control Processor (PCP) This function is controlled by the RPROT register (“Register Protection Register, PCP_RPROT” on Page 87). 10.13.2 Access to the PRAM from the FPI Bus FPI Bus accesses to the PRAM must always be performed with word accesses; byte or half-word accesses will result in a bus error.
Page 732 TC1728 Peripheral Control Processor (PCP) The FPI Bus address of an instruction pointed to by the PCP program counter, PC, is calculated by the following formula: • Effective FPI Bus address[31:0] = (CMEM Base Address) + <PC> << 1 User’s Manual 10-60 V1.0, 2011-12...
Page 733: Debugging The Pcp
TC1728 Peripheral Control Processor (PCP) 10.14 Debugging the PCP For debugging the PCP, a special instruction, DEBUG, is provided. This instruction can only be used when the PCP is in Debug Mode. It can be placed at important locations inside the code to track and trace program execution. The execution of the instruction depends on a condition code specified with the instruction.
Page 734 TC1728 Peripheral Control Processor (PCP) changed by the operation of another active channel. In this case, the required registers should be explicitly saved to PRAM by store instructions prior to execution of the DEBUG instruction. If the DEBUG instruction is programmed to stop all channel program execution, the PCP disables further invocations of any channel by clearing bit PCP_CS.EN.
Page 735: Pcp Registers
TC1728 Peripheral Control Processor (PCP) 10.15 PCP Registers The PCP can be viewed as being a peripheral on the FPI Bus. As with any other peripheral, there are control registers, normally set by the CPU acting as an external FPI Bus master to the PCP during initialization.
Page 736 TC1728 Peripheral Control Processor (PCP) Control Registers Interrupt Registers PCP_CLC PCP_SRC0 PCP_CS PCP_SRC1 PCP_ES PCP_SRC2 PCP_ICR PCP_SRC3 PCP_ITR PCP_SRC4 PCP_ICON PCP_SRC5 PCP_SSR PCP_SRC6 PCP_RPROT PCP_SRC7 PCP_CPROT PCP_SRC8 PCP_PPROT PCP_SRC9 PCP_FWWIN PCP_SRC10 PCP_SMACON PCP_SRC11 PCP_MIECON PCP_MIESTATP PCP_MIESTATC MCA06150 Figure 28 PCP Registers...
Page 737 TC1728 Peripheral Control Processor (PCP) Table 33 Register Overview of PCP Short Name Description Offset Access Mode Reset Description Addr. Read Write PCP_CLC Clock Control U, SV, Page 68 Register 32, E Reset PCP_ID Module Identification U, SV, Page 69...
Page 738 TC1728 Peripheral Control Processor (PCP) Table 33 Register Overview of PCP Short Name Description Offset Access Mode Reset Description Addr. Read Write PCP_CPROT CMEM Protection U, SV, Page 88 Register E, 32 Reset PCP_PPROT PRAM Protection U, SV, Page 89...
Page 739: Pcp Registers Address Space
TC1728 Peripheral Control Processor (PCP) 3) Endinit protection is controlled by the EIE bit. 4) The register is only accessible when the “pcp_sec_con_en_i” input is asserted. Any access to this register when “pcp_sec_con_en_i” is not asserted will generate an FPI error response.
Page 740: Registers
TC1728 Peripheral Control Processor (PCP) 10.17 Registers 10.17.1 PCP Clock Control Register, PCP_CLC PCP_CLC PCP Clock Control Register Reset Value: 0000 0000 Field Bits Type Description [31:16] r Reserved Read as 0; should be written with 0. PCGDIS Clock Gating Disable Bit Allows clock gating to be disabled.
Page 741: Pcp Module Identification Register, Pcp_Id
TC1728 Peripheral Control Processor (PCP) 10.17.2 PCP Module Identification Register, PCP_ID PCP_ID PCP Module Identification Register Reset Value: 0020 C009 MODNUM ID32BIT REVNUM Field Bits Type Description MODNUM [31:16] r PCP Identification Number value = 0020 ID32BIT [15:8] 32-bit Module Identification Number Marker...
Page 742: Pcp Control And Status Register, Pcp_Cs
TC1728 Peripheral Control Processor (PCP) 10.17.3 PCP Control and Status Register, PCP_CS This register can be Endinit-protected via bit EIE. PCP_CS PCP Control/Status Register Reset Value: 0000 0000 EIE RCB RES RS RES EN Field Bits Type Description [31:24] rw Error Service Request Number SRPN for interrupt to CPU on an error condition.
Page 743 TC1728 Peripheral Control Processor (PCP) Field Bits Type Description [15:9] PRAM Partition Size Default, only allowed with PPE = 0 CSA contains 3 context save regions CSA contains 1 + 2 × 127 context save regions Note: The actual size of the CSA (in words) is given by ×...
Page 744: Pcp Error/Debug Status Register, Pcp_Es
TC1728 Peripheral Control Processor (PCP) Field Bits Type Description Channel Start Mode Control Channel resume operation mode selected; channel start PC is taken from restored context Channel restart operation mode selected; channel start PC is derived from the requested channel number (= priority number of service...
Page 745 Memory Error This bit is set if a PCP internal memory error has occurred. See Table 10.22 “Implementation of the PCP in the TC1728” on Page 159 for TC1728 specific implementation. Debug Event Flag Set if the last error/debug event was a debug event.
Page 746: Pcp Interrupt Control Register, Pcp_Icr
TC1728 Peripheral Control Processor (PCP) Field Bits Type Description Disabled Channel Request Flag Set if the last error/debug event was an error generated by receipt of an interrupt request with an SRPN that attempted to start a disabled PCP channel;...
Page 747 TC1728 Peripheral Control Processor (PCP) PCP_ICR PCP Interrupt Control Register Reset Value: 0000 0000 PARBCYC PIPN CPPN Field Bits Type Description [31:27] r Reserved Read as 0; should be written with 0. PONECYC Clocks per Arbitration Cycle Control This bit determines the number of clocks per arbitration cycle.
Page 748 TC1728 Peripheral Control Processor (PCP) Field Bits Type Description Reserved CPPN [7:0] Current PCP Priority Number This field indicates the current priority level of the PCP and is automatically updated by hardware on entry into an interrupt service routine. User’s Manual 10-76 V1.0, 2011-12...
Page 749: Pcp Interrupt Threshold Register, Pcp_Itr
TC1728 Peripheral Control Processor (PCP) 10.17.6 PCP Interrupt Threshold Register, PCP_ITR PCP_ITR PCP Interrupt Threshold Control Register Reset Value: 0000 0000 Field Bits Type Description [31:20] r Reserved Read as 0; should be written with 0. [19:16] rw Interrupt Threshold Level...
Page 750: Pcp Interrupt Configuration Register, Pcp_Icon
Interrupt bus 0 is always enabled. [7:6] PCP Interrupt Bus 3 TOS Mapping This field reflects the TOS associated with interrupt bus 3. Note: Interrupt bus 3 is not available in the TC1728. User’s Manual 10-78 V1.0, 2011-12 PCP, V2.09...
Page 751 PCP Interrupt Bus 2 TOS Mapping This field reflects the TOS associated with interrupt bus 2. Note: Interrupt bus 2 is not available in the TC1728. [3:2] PCP Interrupt Bus 1 TOS Mapping This field reflects the TOS associated with interrupt bus 1 (PCP interrupt arbitration bus).
Page 752: Pcp Stall Status Register, Pcp_Ssr
TC1728 Peripheral Control Processor (PCP) 10.17.8 PCP Stall Status Register, PCP_SSR PCP_SSR PCP Stall Status Register Reset Value: 0000 0000 SCHN STOS SSRN Field Bits Type Description [31:24] Reserved Read as 0. SCHN [23:16] PCP Stalled Channel Number This field shows the channel number of the channel that was executing when the last (or present) stall condition occurred.
Page 753 TC1728 Peripheral Control Processor (PCP) Field Bits Type Description SSRN [7:0] PCP Stalled Service Request Number This field shows the Service Request Number that was being posted when the last (or present) stall condition occurred. This field can only be cleared by a reset.
Page 754: Sist Mode Access Control Register, Pcp_Smacon
TC1728 Peripheral Control Processor (PCP) 10.17.9 SIST Mode Access Control Register, PCP_SMACON Note: Please see Section 10.10 Page 46 for more information regarding the use of this register. This register is ENDINIT protected. PCP_SMACON SIST Mode Access Control Register Reset Value: 0000 0000...
Page 755: Memory Integrity Error Control Register, Pcp_Miecon
TC1728 Peripheral Control Processor (PCP) 10.17.10 Memory Integrity Error Control Register, PCP_MIECON Note: Please see Section 10.11 Page 47 for more information regarding the use of this register. This register is ENDINIT protected. PCP_MIECON SIST Mode Access Control Register Reset Value: 0000 0000...
Page 756: Memory Integrity Error Control 2 Register, Pcp_Miecon2
TC1728 Peripheral Control Processor (PCP) 10.17.11 Memory Integrity Error Control 2 Register, PCP_MIECON2 Note: Please see Section 10.11 Page 47 for more information regarding the use of this register. This register is ENDINIT protected, in addition the register cannot be accessed unless the ““pcp_sec_con_en_i”...
Page 757: Memory Integrity Error Status Register For Pram, Pcp_Miestatp
TC1728 Peripheral Control Processor (PCP) 10.17.12 Memory Integrity Error Status Register for PRAM, PCP_MIESTATP Note: Please see Section 10.11 Page 47 for more information regarding the use of this register. PCP_MIESTATP Memory Integrity Error Status Register for PRAM(58 Reset Value: 0000 0000...
Page 758: Memory Integrity Error Status Register For Cmem, Pcp_Miestatc
TC1728 Peripheral Control Processor (PCP) 10.17.13 Memory Integrity Error Status Register for CMEM, PCP_MIESTATC Note: Please see Section 10.11 Page 47 for more information regarding the use of this register. PCP_MIESTATC Memory Integrity Error Status Register for CMEM(5C Reset Value: 0000 0000...
Page 759: Register Protection Register, Pcp_Rprot
TC1728 Peripheral Control Processor (PCP) 10.17.14 Register Protection Register, PCP_RPROT This register is ENDINIT protected. PCP_RPROT Register Protection Register Reset Value: 0000 0000 Field Bits Type Description Register Protection Enable Registers are not protected and can be written at any time.
Page 760: Cmem Protection Register, Pcp_Cprot
TC1728 Peripheral Control Processor (PCP) 10.17.15 CMEM Protection Register, PCP_CPROT Note: Please see Section 10.13.3 Page 59 for more information regarding the use of this register. This register is ENDINIT protected. PCP_CPROT CMEM Protection Register Reset Value: 0000 0000 Field...
Page 761: Pram Protection Register, Pcp_Pprot
TC1728 Peripheral Control Processor (PCP) 10.17.16 PRAM Protection Register, PCP_PPROT This register is ENDINIT protected. PCP_PPROT PRAM Protection Register Reset Value: 0000 0000 PTHRES PSIZE FBASE Field Bits Type Description PRAM Protection Enable for FPI Writes PRAM is not protected and can be written via FPI at any time.
Page 762 TC1728 Peripheral Control Processor (PCP) Field Bits Type Description PRAM Protection Enable for Internal Writes The entire PRAM (subject to PRAM partitioning) is not protected and can be written using PCP PRAM write instructions. All PRAM outside the Protected Window (and...
Page 763 TC1728 Peripheral Control Processor (PCP) Field Bits Type Description PTHRES [23:16] Protected Channel Threshold When PPROT.ENI is ‘0’, this field has no effect. When PPROT.ENI is ‘1’, this field defines the Channel number which is used to distinguish between protected and non-protected Channels.
Page 764 TC1728 Peripheral Control Processor (PCP) Field Bits Type Description FBASE [7:0] PRAM FPI Open Window Base When PPROT.EN is ‘0’, this field has no effect. When PPROT.EN is '1' (see above) this field defines the base address (in multiples of 256 bytes and relative to the base of PRAM) of the region at the top of PRAM that remains writable by FPI writes.
Page 765: Fpi Write Window Register, Pcp_Fwwin
TC1728 Peripheral Control Processor (PCP) 10.17.17 FPI Write Window Register, PCP_FWWIN Note: Please see Section 10.8.1 Page 42 for more information regarding the use of this register. This register is ENDINIT protected. PCP_FWWIN FPI Write Window Register Reset Value: 0000 0000...
Page 766: Pcp Service Request Control Registers M, Pcp_Src[1:0]
TC1728 Peripheral Control Processor (PCP) Field Bits Type Description SIZE [28:24] Window Size The FPI window size (binary sizing) 256 bytes 512 bytes (n+8) bytes BASE [23:0] Window Base Address Controls the base address of the FPI window (binary aligned according to the window size. Bit 23 maps to the bit 31 of the FPI byte address.
Page 767 TC1728 Peripheral Control Processor (PCP) Field Bits Type Description PCP Node m Service Request Flag No service requested (default). Valid active service requested. PCP Node m Service Request Enable Always read as 1 (enabled). [11:10] PCP Node m Type-of-Service State Always read as 00 .
Page 768: Pcp Service Request Control Registers M, Pcp_Src[3:2]
TC1728 Peripheral Control Processor (PCP) 10.17.19 PCP Service Request Control Registers m, PCP_SRC[3:2] Service request nodes for interrupt bus 1 (PCP interrupt arbitration bus). PCP_SRCm (m = 2-3) PCP Service Request Control Register m -m*4 Reset Value: 0000 1400 SRPN...
Page 769: Pcp Service Request Control Registers M, Pcp_Src[8:4]
TC1728 Peripheral Control Processor (PCP) 10.17.20 PCP Service Request Control Registers m, PCP_SRC[8:4] Service request nodes programmable for interrupt bus 0 (CPU interrupt arbitration bus) or 1 (PCP interrupt arbitration bus). PCP_SRCm (m = 4-8) PCP Service Request Control Register m...
Page 770: Pcp Service Request Control Registers M, Pcp_Src[11:9]
TC1728 Peripheral Control Processor (PCP) Field Bits Type Description SRPN [7:0] PCP Node m Service Request Priority Number This number is automatically set by the PCP if it needs to place a service request on interrupt bus 0 (CPU interrupt arbitration bus) or 1 (PCP interrupt arbitration bus).
Page 771 TC1728 Peripheral Control Processor (PCP) Field Bits Type Description SRCN [23:16] PCP Node m Service Request Channel Number Channel Number Entry (default = 0). When the PCP interrupt request was raised by the PCP Processor Core when executing an EXIT instruction, then this bit field contains the SRPN value taken from R6 when the exit instruction was executed.
Page 772: Pcp Instruction Set Details
TC1728 Peripheral Control Processor (PCP) 10.18 PCP Instruction Set Details This section describes the instruction set architecture of the PCP in detail. 10.18.1 Instruction Codes and Fields All PCP instructions use a common set of fields to describe such things as the source register, and the state of flags.
Page 773: Conditional Codes
TC1728 Peripheral Control Processor (PCP) 10.18.1.1 Conditional Codes Many PCP instructions have the option of being executed conditionally. The condition code of an instruction is the field that specifies the condition to be tested before the instruction is executed. Depending on the type of instruction there are 8 or 16 condition codes available.
Page 774: Instruction Fields
TC1728 Peripheral Control Processor (PCP) 10.18.1.2 Instruction Fields Table 36 lists the instruction field definitions of the PCP instruction set architecture. Note: The exact syntax for these fields may be different depending on which tool (e.g. assembler) is used. Please refer to the respective tool descriptions.
Page 775 TC1728 Peripheral Control Processor (PCP) Table 36 Instruction Field Definitions Symbol Syntax Description Stop PCP DAC = 0 Allow the PCP to continue to execute channel programs in response to service requests. DAC = 1 Prevent the PCP from executing further channel programs (PCP_CS.EN = 0).
Page 776 TC1728 Peripheral Control Processor (PCP) Table 36 Instruction Field Definitions Symbol Syntax Description SIZE Data Size Control SIZE = 00 Byte (8-bit) SIZE = 01 Half-word (16-bit) SIZE = 10 Word (32-bit) SIZE = 11 Reserved SRC+- Source Address Pointer Control...
Page 777: Counter Operation For Copy Instruction
TC1728 Peripheral Control Processor (PCP) 10.18.2 Counter Operation for COPY Instruction Figure 10 - 1 shows the flow of a COPY instruction. COPY Instruction t_count := CNT0 DATA Transfer t_count := t_count - 1 t_count = 0 ? CNC = ?
Page 778: Counter Operation For Bcopy Instruction
TC1728 Peripheral Control Processor (PCP) 10.18.3 Counter Operation for BCOPY Instruction Figure 10 - 2 shows the flow of a BCOPY instruction. BCOPY Instruction DATA Transfer (Block size determined by CNT0 field) CNC = ? CNT1 := CNT1 - 1...
Page 779: Divide And Multiply Instructions
TC1728 Peripheral Control Processor (PCP) 10.18.4 Divide and Multiply Instructions The PCP has Multiply and Divide capabilities (unsigned values only). All Multiply and divide instructions operate on 8 bits of data (taken from the dividend for divide, from the multiplicand for multiply). This strategy allows the user to implement the appropriate number of instructions (“steps”) as required for the user’s data format.
Page 780: Add, 32-Bit Addition
TC1728 Peripheral Control Processor (PCP) a 40-bit unsigned multiply and then shifts this result right by 8 bits (discards the least significant 8 bits of the 40-bit result). The DSTEP instruction also has some conditions stipulated regarding input values to the instruction.
Page 781: And, 32-Bit Logical And
TC1728 Peripheral Control Processor (PCP) 10.18.6 AND, 32-bit Logical AND This section describes the AND instructions of the PCP. Syntax AND Rb, Ra, cc_A Description If the condition CONDCA is true, then perform a bit-wise logical AND of the contents of register Ra and the contents of register Rb;...
Page 782: Bcopy, Dma Operation
TC1728 Peripheral Control Processor (PCP) 10.18.7 BCOPY, DMA Operation This section describes the BCOPY instruction of the PCP in the TC1728. BCOPY Syntax BCOPY DST+-, SRC+-, CNC, CNT0 Description Allows the PCP to perform DMA type transfers using FPI block transfers.
Page 783: Chkb, Check Bit
TC1728 Peripheral Control Processor (PCP) 10.18.8 CHKB, Check Bit This section describes the CHKB instruction of the PCP. CHKB Syntax CHKB Ra, #imm5, S/C Description If bit imm5 of register Ra is equal to the specified test value S/C then set the carry flag R7.C, else clear the carry flag.
Page 784: Comp, 32-Bit Compare
TC1728 Peripheral Control Processor (PCP) 10.18.10 COMP, 32-bit Compare This section describes the COMP instructions of the PCP. COMP Syntax COMP Rb, Ra, cc_A Description If the condition CONDCA is true, then subtract the contents of register Ra from the contents of register Rb; set the flags in register R7 according to the result of the subtraction;...
Page 785: Copy, Dma Instruction
TC1728 Peripheral Control Processor (PCP) 10.18.11 COPY, DMA Instruction This section describes the COMP instruction of the PCP. COPY Syntax COPY DST+-, SRC+-, CNC, CNT0, SIZE Description Moves the contents of FPI Bus source location to FPI Bus destination location. Source location is pointed to by the contents of register R4;...
Page 786: Debug, Debug Instruction
TC1728 Peripheral Control Processor (PCP) 10.18.12 DEBUG, Debug Instruction This section describes the DEBUG instruction of the PCP. DEBUG Syntax DEBUG EDA, DAC, RTA, SDB, cc_B Description Conditionally cause a debug event if condition CONDCB is true. Optionally stop channel execution (SDB = 1) and/or generate an external debug event (EDA = 1).
Page 787: Dinit, Divide Initialization
TC1728 Peripheral Control Processor (PCP) 10.18.13 DINIT, Divide Initialization This section describes the DINIT instruction of the PCP. DINIT Syntax DINIT <R0>, Rb, Ra Description Initialize Divide logic ready for divide sequence (Rb / Ra) and Clear R0. If value of Ra is 0 then set V (to flag divide by 0 error);...
Page 788: Dstep, Divide Instruction
TC1728 Peripheral Control Processor (PCP) 10.18.14 DSTEP, Divide Instruction This section describes the DSTEP instruction of the PCP. DSTEP Syntax DSTEP <R0>, Rb, Ra Description Perform 1 step (eight bits) of an unsigned 32- by 32-bit divide (Rb / Ra). Shift R0 left by 8 bits, copy the most significant byte of Rb into LS byte of R0.
Page 789: Exit, Exit Instruction
TC1728 Peripheral Control Processor (PCP) 10.18.15 EXIT, Exit Instruction This section describes the EXIT instruction of the PCP. EXIT Syntax EXIT EC, ST, INT, EP, cc_B Description Unconditionally exit channel program execution. Optionally decrement counter CNT1 (EC = 1), disable further channel invocation (ST = 1), generate an interrupt request (INT = 1) if condition CONDCB is true.
Page 790: Inb, Insert Bit
TC1728 Peripheral Control Processor (PCP) 10.18.16 INB, Insert Bit This section describes the INB instructions of the PCP. Syntax INB Rb, Ra, cc_A Description If CONDCA is true, then insert the carry flag R7.C into register Rb at the bit position specified through bits [4..0] of register Ra.
Page 791: Jc, Jump Conditionally
TC1728 Peripheral Control Processor (PCP) 10.18.17 JC, Jump Conditionally This section describes the conditional jump instructions of the PCP. Syntax JC offset6, cc_B Description If CONDCB is true, then add the sign-extended value specified by offset6 to the contents of the PC, and jump to that address.
Page 792: Jl, Jump Long Unconditional
TC1728 Peripheral Control Processor (PCP) 10.18.18 JL, Jump Long Unconditional This section describes the long jump instruction JL of the PCP. Syntax JL offset10 Description Add the sign-extended value specified by offset10 to the contents of the PC, and jump to that address.
Page 793 TC1728 Peripheral Control Processor (PCP) LD.P Syntax LD.P Rb, [Ra], cc_A Description If condition CONDCA is true, then load the contents of the PRAM address location, specified by the addition of contents of the PRAM Data Pointer, shifted left by six bits, and the zero-extended 6-bit value Ra[5:0] into register Rb.
Page 794: Ldl, Load 16-Bit Value
TC1728 Peripheral Control Processor (PCP) 10.18.20 LDL, Load 16-bit Value This section describes the LDL instructions of the PCP. LDL.IL Syntax LDL.IL Ra, #imm16 Description Load the immediate value imm16 into the lower bits of register Ra (bits [15:0]). Bits [31:16] of register Ra are unaffected.
Page 795: Mov, Move Register To Register
TC1728 Peripheral Control Processor (PCP) 10.18.22 MOV, Move Register to Register This section describes the MOV instruction of the PCP. Syntax MOV Rb, Ra, cc_A Description If condition CONDCA is true, then move the contents of register Ra into register Rb. If CONDCA is false, no operation is performed.
Page 796: Multiply Instructions
TC1728 Peripheral Control Processor (PCP) 10.18.23 Multiply Instructions This section describes the multiply instructions of the PCP. MSTEP32 Syntax MSTEP32 <R0>, Rb, Ra Description Perform an unsigned multiply step, using eight bits of data taken from Rb, keeping the least significant 32 bits of a potential 64-bit result.
Page 797: Neg, Negate
TC1728 Peripheral Control Processor (PCP) 10.18.24 NEG, Negate This section describes the NEG instruction of the PCP. Syntax NEG Rb, Ra, cc_A Description If condition CONDCA is true, then move the 2’s complement of the contents of register Ra into register Rb. If CONDCA is false, no operation is performed.
Page 798: Or, Logical Or
TC1728 Peripheral Control Processor (PCP) 10.18.27 OR, Logical OR This section describes the OR instructions of the PCP. Syntax OR Rb, Ra, cc_A Description If the condition CONDCA is true, then perform a bit-wise logical OR of the contents of register Ra and the contents of register Rb;...
Page 799: Pram Bit Operations
TC1728 Peripheral Control Processor (PCP) 10.18.28 PRAM Bit Operations This section describes the MCLR and MSET instructions of the PCP. MCLR Syntax MCLR.PI Ra, [#offset6] Description Perform an ‘AND’ of the contents of the specified register with the contents of the PRAM location specified by the addition of contents of the PRAM Data Pointer, shifted left by six bits, and the zero-extended 6-bit value offset.
Page 800: Pri, Prioritize
TC1728 Peripheral Control Processor (PCP) 10.18.29 PRI, Prioritize This section describes the PRI instruction of the PCP. PRId Syntax PRI Rb, Ra, cc_A Description If condition CONDCA is true, then find the bit position of the most significant 1 in register Ra and put the number into register Rb.
Page 801: Rl, Rotate Left
TC1728 Peripheral Control Processor (PCP) 10.18.30 RL, Rotate Left This section describes the RL instruction of the PCP. Syntax RL Ra, #imm5 Description Rotate the contents of register Ra to the left by the number of bit positions specified through the 5-bit value imm5. The values defined for imm5 are 1, 2, 4 and 8.
Page 802: Set, Set Bit
TC1728 Peripheral Control Processor (PCP) 10.18.32 SET, Set Bit This section describes the SET bit instruction of the PCP. Syntax SET Ra, #imm5 Description Set bit imm5 of register Ra to 1. Operation R[a][imm5] = 1 Flags None SET.F Syntax SET.F [Ra], #imm5, Size...
Page 803: Shr, Shift Right
TC1728 Peripheral Control Processor (PCP) 10.18.34 SHR, Shift Right This section describes the SHR instruction of the PCP. Syntax SHR Ra, #imm5 Description Shift the contents of register Ra to the right by the number of bit positions specified through the 5-bit value imm5. The values allowed for imm5 are 1, 2, 4 and 8.
Page 804: St, Store
TC1728 Peripheral Control Processor (PCP) 10.18.35 ST, Store This section describes the ST instructions of the PCP. ST.F Syntax ST.F Rb, [Ra], Size Description Store the contents of register Rb to the address location specified by the contents of register Ra. When the Size is byte or half-word, the data is stored with the internal LSB (bit 0) properly aligned to the correct FPI Bus byte or half-word lane.
Page 805: Sub, 32-Bit Subtract
TC1728 Peripheral Control Processor (PCP) 10.18.36 SUB, 32-bit Subtract This section describes the SUB instructions of the PCP. Syntax SUB Rb, Ra, cc_A Description If the condition CONDCA is true, then subtract the contents of register Ra from the contents of register Rb; place the result in Rb.
Page 806: Xch, Exchange
TC1728 Peripheral Control Processor (PCP) 10.18.37 XCH, Exchange This section describes the XCH instructions of the PCP. XCH.F Syntax XCH.F Rb, [Ra], Size Description Exchange contents of R[b] and FPI[R[a]] when Size is byte or half-word, the value is stored with the internal LSB (bit 0) properly aligned to the correct FPI byte or half-word lane.
Page 807: Xor, 32-Bit Logical Exclusive Or
TC1728 Peripheral Control Processor (PCP) 10.18.38 XOR, 32-bit Logical Exclusive OR This section describes the XOR instructions of the PCP. Syntax XOR Rb, Ra, cc_A Description If the condition CONDCA is true, then perform a bit-wise logical Exclusive-OR of the contents of register Ra and the contents of register Rb;...
Page 808: Flag Updates Of Instructions
TC1728 Peripheral Control Processor (PCP) 10.18.39 Flag Updates of Instructions Most instructions update the state flags in R7. In Table 37, each instruction is shown with the flags that it updates. Table 37 Flag Updates Instruction CN1Z – – –...
Page 809: Instruction Timing
(resulting in a minimum PCP core clock cycle time of 5.6ns). When running in 1:1 clocking mode the maximum PCP core clock frequency is the same as the maximum System Peripheral Bus frequency. In the TC1728 the System Peripheral Bus (which is an FPI Bus) is clocked with f , resulting in a minimum PCP core clock cycle time of 11.1ns (in 1:1 clocking mode).
Page 810 TC1728 Peripheral Control Processor (PCP) Table 38 Instruction Timing Instruction Number of Clock Cycles Comments Notes COPY – – EXIT f = 9, s = 7, m = 6 – BCOPY – – FPI Access ADD.F 8 min. 5 int. + 3 min.
Page 811 TC1728 Peripheral Control Processor (PCP) Table 38 Instruction Timing Instruction Number of Clock Cycles Comments Notes LD.P – – – – – – – – – – – – ST.P – – – – – – Immediate Access ADD.I –...
Page 812 TC1728 Peripheral Control Processor (PCP) Table 38 Instruction Timing Instruction Number of Clock Cycles Comments Notes Complex Math DINIT – DSTEP – MINIT – MSTEP.L – MSTEP.U – Jump DEBUG sdb - 0 = 2 – sdb - 1 = exit_time y = 4, n = 2 –...
Page 813: Instruction Encoding
TC1728 Peripheral Control Processor (PCP) 10.19 Instruction Encoding Most instructions are encoded in 16 bits. This allows two instruction to be fetched out of 32 bit instruction memory per access. For example, a COPY and an EXIT instruction can be fetched simultaneously, performing a simple DMA transaction.
Page 814 TC1728 Peripheral Control Processor (PCP) Table 39 Field Definitions Symbol Name Description Exit Count no action Control decrement CNT1 External Debug No External Debug Action caused Action Cause an External Debug Action (breakpoint pin etc.) Entry Point Entry Point on next Channel Invocation:...
Page 815 TC1728 Peripheral Control Processor (PCP) Table 40 Instruction Encoding 0 -:Control fmt Ins DST + - SRC + - CNT0 Size COPY INT EP EC - CONDC B EXIT Condition for Interrupt fmt Ins DST + - SRC + -...
Page 816 TC1728 Peripheral Control Processor (PCP) Table 40 Instruction Encoding error MCLR.PI AND.PI MSET.PI OR.PI XOR.PI LD.PI ST.PI XCH.PI error error error error 3 -:Arithmetic Instruction R[b] R[a] CONDC A COMP error LD.P ST.P error error User’s Manual 10-144 V1.0, 2011-12...
Page 817 TC1728 Peripheral Control Processor (PCP) Table 40 Instruction Encoding 4 - Immediate Instruction R[a] Immediate 6 - bit SUB.I ADD.I COMP.I error LDL.IU following #imm16 instruction LDL.IL following #imm16 instruction LD.I INB.I CHKB error 5 -:FPI Instruction R[a] Immediate 5 - bit...
Page 818 TC1728 Peripheral Control Processor (PCP) Table 40 Instruction Encoding MINIT MSTEP.L MSTEP.U error error error error error error error error error error error 7 -:JUMP op2:Instr Offset 10 - bit op2:Instr CONDC B Offset 6 - bit JC.A Absolute Destination in next...
Page 819: Programming Of The Pcp
TC1728 Peripheral Control Processor (PCP) 10.20 Programming of the PCP In this section, several techniques are outlined to help design channel programs. There are also examples on configuring a channel program’s context. 10.20.1 Initial PC of a Channel Program A channel program can begin operation at the Channel Entry Table location corresponding to the priority of the interrupt.
Page 820: Channel Resume
TC1728 Peripheral Control Processor (PCP) 10.20.1.2 Channel Resume When PCP_CS.RCB = 0, the program counter of the PCP is vectored to the address that is restored from the channel program’s context. This means that before exiting, a channel program must itself arrange for where it will resume execution by configuring the value of its PC in its saved context so that it restarts at the desired location.
Page 821: Channel Management For Small And Minimum Contexts
TC1728 Peripheral Control Processor (PCP) ERROR,cc_NZ ;jump to error routine ;if not correct ADD.I R5,#0x1 ;increment state number EXIT EC=1,ST=0,INT=0,EP=1,cc_UC ;begin exit STATE1: COMP.I R5,#0x1 ;compare to interrupt number ;it should be ERROR,cc_NZ ;jump to error routine ;if not correct ADD.I...
Page 822: Dispatch Of Low Priority Tasks
TC1728 Peripheral Control Processor (PCP) two choices here. A boot-time interrupt channel program can be invoked once to perform initialization, or there can be a program that routinely loads these values as a matter of course, and is invoked at boot time or as upon receipt of the very first interrupt.
Page 823: Case-Like Code Switches (Computed Go-To)
TC1728 Peripheral Control Processor (PCP) 10.20.6 Case-like Code Switches (Computed Go-To) The JC.I instruction can be used to implement a multi-way branch for branch-on-bit or branch-on-state conditional branches. This instruction allows a conditional relative jump based on an index held in a register. If this instruction is combined with a table of jump addresses, a switch-type statement can be implemented.
Page 824: Bcopy Instruction (Burst Copy)
(see the FPI Bus description for details). If either address is incorrectly aligned, the PCP will generate an Illegal Operation Error Exit. See also Page 159 for TC1728 specific details of the BCOPY instruction. User’s Manual 10-152 V1.0, 2011-12...
Page 825: Pcp Programming Notes And Tips
TC1728 Peripheral Control Processor (PCP) 10.21 PCP Programming Notes and Tips This section discusses constraints on the use of the PCP and points out some non- obvious issues. 10.21.1 Notes on PCP Configuration For configuring of the PCP, some notes should be regarded.
Page 826 TC1728 Peripheral Control Processor (PCP) TOS (service request number to use during optional interrupt at channel program EXIT) fields, R6 should not be used to pass values from one invocation of a channel program to the next invocation. • If PRAM is to be accessed programmatically, then R7.DPTR must be configured properly as a pointer into the PRAM.
Page 827: Use Of Channel Interruption
TC1728 Peripheral Control Processor (PCP) 10.21.3 Use of Channel Interruption For channel interruption, the following note should be regarded. • When a channel program consists of only a few instructions, it is best to configure the channel to be non-interruptible. This increases overall efficiency by removing the context save/restore overhead that would be incurred if the channel were to be interruptible.
Page 828: Implementing Divide Algorithms
TC1728 Peripheral Control Processor (PCP) Note: When using this scheme, each channel program must ensure prior to channel exit that the R6.CPPN field contains the appropriate value, so that when the channel is next invoked, it will run at the correct priority.
Page 829: Implementing Multiply Algorithms
TC1728 Peripheral Control Processor (PCP) instructions in the sequence) but the divisor is always 32 bits. Prior to the DINIT instruction, the dividend must always occupy the appropriate most significant bits within the 32-bit dividend register (Rb). Divide Examples Example of a 32/32 bit divide (R5 / R3):...
Page 830 TC1728 Peripheral Control Processor (PCP) R1, 8 ;Rotate least significant byte of R1 ;to most significant byte MINIT R1, R4 ;Initialize ready for multiply MSTEP32 R1, R4 ;Perform one MSTEP32 instruction ;(8 bit multiply) After this sequence, R0 holds the result, R1 is left unchanged (right rotated by RR instruction then left rotated by MSTEP32 instruction), and R4 is unchanged.
Page 831: Implementation Of The Pcp In The Tc1728
The addresses of the PCP registers and memories in the TC1728 are given in the following subsections: 10.22.1 PCP Memories In the TC1728, the location of the registers and the memories sizes of the PRAM and the CMEM are given in Table Table 41...
Page 832: Pcp Reset Operation
PCP Reset Operation The PCP module can be reset by a system hardware signal (hard reset). PCP Hard Reset A PCP hard reset is always triggered if at least one of these TC1728 reset sources becomes active: • Watchdog Timer Reset •...
Page 833: Direct Memory Access Controller (Dma)
Direct Memory Access Controller (DMA) Direct Memory Access Controller (DMA) This chapter describes the Direct Memory Access (DMA) Controller and the Memory Checker Module (MCHK) of the TC1728. It contains the following sections: • Functional description of the DMA controller kernel (see Section 11.2)
Page 834 TC1728 Direct Memory Access Controller (DMA) • The System Interrupt Registers are removed from the DMA module (moved to CPU, SCU and PMU). • The DMA module has now 8 Service Requests nodes in general. DMA interrupt outputs DMA SR[7:0] are connected to interrupt nodes. SR[15:8] are used as DMA channel request inputs (DMA_SRCn (n = 0-7)).
Page 835: Dma Controller Kernel Description
DMA Sub-Block. The Bus Switch provides the connection of the DMA Sub-Blocks to the two On Chip Bus interfaces and a DMA Peripheral interface. In the TC1728, the two On Chip Bus interfaces are connected to the System Peripheral Bus and the LMB Bus.
Page 836: Features
TC1728 Direct Memory Access Controller (DMA) 11.2.1 Features The DMA controller has the following features: • 16 independent DMA channels – 2 DMA Sub-Blocks with (8 DMA channels per DMA Sub-Block) – DMA Sub-Blocks with support of parallel channel execution (1 channel per Sub- Block, both Sub-Blocks in parallel) –...
Page 837: Definition Of Terms
TC1728 Direct Memory Access Controller (DMA) 11.2.2 Definition of Terms Some basic terms must be defined for the functional description of the DMA controller. DMA Move A DMA move is an operation that always consists of two parts: 1. A read move that loads data from a data source into the DMA controller 2.
Page 838: Dma Principles
TC1728 Direct Memory Access Controller (DMA) 11.2.3 DMA Principles The DMA controller supports DMA moves from one address location to another one. DMA moves can be requested either by hardware or by software. DMA hardware requests are triggered by specific request lines from the peripheral modules or from...
Page 839: Dma Channel Functionality
TC1728 Direct Memory Access Controller (DMA) 11.2.4 DMA Channel Functionality Each of the 16 DMA channels has one associated register set containing seven 32-bit registers. These registers are numbered by one index to indicate the related DMA Sub- Block and one index to indicate the related DMA channel: Index “m” refers to the DMA Sub-Block number (m = 0-1) and Index “n”...
Page 840 TC1728 Direct Memory Access Controller (DMA) When writing a new address to the (address of) the source or destination address register and no DMA transaction is running, the new address value is directly written into the source or destination address register. In this case, no buffering of the address is required.
Page 841 TC1728 Direct Memory Access Controller (DMA) Write new source address to (address of ) SADRmn Transaction running ? (CHSRmn.TCOUNT != 0 OR TRSR.CHmn = 1) Store new source address intermediately in SHADRmn New transaction started ? & (ADRCRmn.SHCT = 01 Content of SHADR0n is transferred into SADRmn .
Page 842 TC1728 Direct Memory Access Controller (DMA) CHSRmn.TCOUNT tc2-1 tc2-2 tc1-1 CHCRmn.TREL sa1+ sa1+ SADRmn sa1+1 sa2+1 sa2+2 tc1-1 SHADRmn with 0000 0000 ADRCRmn.SHCT= 01 tc1 = transfer count 1 1) 3) = writing to CHCRmn and SADRmn tc2 = transfer count 2...
Page 843: Dma Channel Request Control
TC1728 Direct Memory Access Controller (DMA) 11.2.4.2 DMA Channel Request Control Figure 11-6 shows the control logic for DMA requests that is implemented for each DMA channel. CHCRmn Suspend Request CHMODE TRSR Suspend Control HTREQ TRSR & SUSPMR Reset ECHmn...
Page 844: Dma Channel Operation Modes
TC1728 Direct Memory Access Controller (DMA) Status flag TRSR.CHmn indicates whether or not a software or hardware generated DMA request for DMA channel mn is pending. TRSR.CHmn can be reset by software or by hardware at the end of a DMA transfer (RROAT = 0) or at the end of a DMA transaction (RROAT = 1).
Page 845 TC1728 Direct Memory Access Controller (DMA) When TCOUNT reaches the 0, DMA channel mn becomes disabled and status flag TRSR.CHmn is reset. Setting STREQ.SCHmn again starts a new DMA transaction of DMA channel mn with the parameters as actually defined in the channel register set.
Page 846 TC1728 Direct Memory Access Controller (DMA) Hardware-controlled Modes In hardware-controlled modes, a hardware request signal starts a DMA transaction or a single DMA transfer. There are two hardware-controlled modes available: • Single Mode: Hardware requests are disabled by hardware after a DMA transaction •...
Page 847 TC1728 Direct Memory Access Controller (DMA) CHCRmn.RROAT = 1 TRSR.CHmn TRSR.HTREmn CHmn_REQ DMA Transfer mn TR0 TR1 TR0 TR1 CHSRmn.TCOUNT tc-1 tc-1 tc = initial transfer count (triggered at the end of a transaction with IRDV=0) CHCRmn.RROAT = 0 TRSR.CHmn TRSR.HTREmn...
Page 848: Error Conditions
TC1728 Direct Memory Access Controller (DMA) Combined Software/Hardware-controlled Mode Figure 11-9 shows how software- and hardware-controlled modes can be combined. In the example, the first DMA transfer is triggered by software when setting STREQ.SCHmn. Hardware requests are still disabled. After hardware requests have been enabled by setting HTREQ.ECHmn, subsequent DMA transfers are triggered now...
Page 849: Channel Reset Operation
TC1728 Direct Memory Access Controller (DMA) The transaction lost error flag ERRSR.TRLmn indicates if a DMA request for a DMA channel mn has been lost. In the case of a read error, the write action is not executed, but the destination address is updated.
Page 850: Transfer Count And Move Count
TC1728 Direct Memory Access Controller (DMA) 11.2.4.6 Transfer Count and Move Count The move count determines the number of moves (consisting of one read and one write each) to be done in each transfer. It allows the user to indicate to the DMA the number of moves to be done after one request.
Page 851 TC1728 Direct Memory Access Controller (DMA) Source Memory Destination Memory Moves ..ADRCRmn Parameters : ADRCRmn Parameters : SMF = 011 DMF = 010 INCS = 1 INCD = 0 MCA06159 Figure 11-11 Programmable Address Modification - Example 1 (m = 0-1)
Page 852: Circular Buffer
TC1728 Direct Memory Access Controller (DMA) Source Memory Destination Memory Moves ADRCRmn Parameters : ADRCRmn Parameters : SMF = 000 DMF = 001 INCS = 1 INCD = 1 MCA06160 Figure 11-12 Programmable Address Modification - Example 2 (m = 0-1) 11.2.4.7 Circular Buffer...
Page 853: Transaction Control Engine
TC1728 Direct Memory Access Controller (DMA) 11.2.5 Transaction Control Engine Each DMA Sub-Block has a Transaction Control Unit. The Transaction Control Unit in the DMA Sub-Block, as shown in the DMA Controller block diagram in Figure 11-1, contains a Channel Arbiter and a Move Engine.
Page 854: Bus Switch, Bus Switch Priorities
TC1728 Direct Memory Access Controller (DMA) DMA Channels 0n of Sub-Block m DMA Channel Arbiter Move Engine m Transaction Control Unit m Bus Switch MCA06161 Figure 11-13 Transaction Control Engine (m = 0-1) 11.2.6 Bus Switch, Bus Switch Priorities The Bus Switch of the DMA controller provides the connection from the DMA Sub-Blocks...
Page 855 TC1728 Direct Memory Access Controller (DMA) DMA Sub-Block m Move Engine m MLI0 Arbiter/ Memory Bus Switch Switch Checker Control Cerberus Buffer Buffer LMB Bus FPI Bus Interface Interface MCA06162 Figure 11-14 Bus Switch One access can be buffered in the bus interfaces.
Page 856: Dma Module Priorities On On Chip Busses (Fpi Bus, Lmb Bus)
TC1728 Direct Memory Access Controller (DMA) CHCRmn.DMAPRIO value determines the priority on the DMA Bus Switch (see Table 11-2). Table 11-1 DMA Bus Switch Priorities Priority Agent Requests Comment Highest Cerberus to On Chip Bus High Priority selection by software in Cerberus.
Page 857: Dma Module: On Chip Bus Access Rights, Rmw Support
TC1728 Direct Memory Access Controller (DMA) The DMA Module is connected to the FPI Bus and to the LMB Bus with master interfaces. The DMA LMB Master and the DMA FPI Master is each connected with three priorities to its On Chip Bus (low, medium and high priority), where it competes against the other bus masters connected to the On Chip Bus for bus access.
Page 858 TC1728 Direct Memory Access Controller (DMA) The DMA FPI master interface supports: • single data read and write transactions (8bit, 16bit, 32bit) • generation of pipelined FPI transactions from different sources (Move Engines, Cerberus, MLI) • de-assertion of request after retry in order to prevent bus blocking.
Page 859: Dma Module Bridge Functionality
TC1728 Direct Memory Access Controller (DMA) If the next read to a read from a segment 8 address is not identical (64bit aligned) to the actual read buffer contents, the contents of the read buffer is invalidated. A 64bit LMB...
Page 860: On-Chip Debug Capabilities
Peripheral Interface is described in the related module chapters. 11.2.11.2 Soft-suspend Mode The TC1728 on-chip debug control unit is able to generate a Soft-suspend Mode request (SUSREQ) for the DMA controller. When this soft-suspend request becomes active, the state of a DMA channel becomes frozen regarding hardware changes to ensure that the state of the DMA channels can be analyzed by reading the register contents.
Page 861: Break Signal Generation
TC1728 Direct Memory Access Controller (DMA) after Suspend Mode has been left again. Suspend Mode of DMA channel mn is left and its normal operation continues if either the SUSREQ signal becomes inactive, or if the enable bit SUSENmn is reset by software.
Page 862 TC1728 Direct Memory Access Controller (DMA) OCDSR DMA Sub-Block m BRL0 ≥1 Enabled & Transaction Lost Interrupts 00-07 ≥1 OCDSR OCDSR BREAK BCHS0 BTCR0 TRSR CH01 Edge Detection TRSR CH07 MCA06164 Figure 11-16 DMA Break Event Generation (m = 0-1) User’s Manual...
Page 863: Interrupts
10-bit TCOUNT value. This means that a TCOUNT match interrupt can be generated after one of the last 16 DMA transfers of a DMA transaction. Note that with 1) In the TC1728, only SR[7:0] are connected to interrupt nodes. SR[8:15] are used for DMA channel triggering/connections.
Page 864 Enabled if PATSEL ≠ 00 Pattern Detection Interrupt mn MCA06165 Figure 11-17 Channel Interrupts (m = 0-1) 1) In the TC1728, SR[7:0] are connected to interrupt nodes. SR[8:15] are used for DMA channel triggering/connections. User’s Manual 11-32 2011-12 DMA, V1.0...
Page 865: Transaction Lost Interrupt
Reset CTL07 TRL07 ETRL07 CH07 Reset Transaction Lost Interrupt 07 MCA06166 Figure 11-18 Transaction Lost Interrupt 1) In the TC1728 SR[7:0] are connected to interrupt nodes. SR[15:8] are used as DMA channel trigger signals. User’s Manual 11-33 2011-12 DMA, V1.0...
Page 866: Move Engine Interrupts
Reset CME0DER ME0DER EME0DER Move Engine 0 Destination Error MCA06167 Interrupt Figure 11-19 Move Engine Interrupts 1) In the TC1728 SR[7:0] are connected to interrupt nodes. SR[15:8] are used as DMA channel trigger signals. User’s Manual 11-34 2011-12 DMA, V1.0...
Page 867 TC1728 Direct Memory Access Controller (DMA) When a Move Engine 0 source or destination error occurs, additional status bits and bit fields are provided in the error status register ERRSR to indicate the following two status conditions: • At which On Chip Bus interface a Move Engine 0 error occurred (FPI or LMB) •...
Page 868: Wrap Buffer Interrupts
WRPDE Reset Wrap Destination Buffer Interrupt 0n MCA06168 Figure 11-20 DMA Wrap Buffer Interrupts(m = 0-1) 1) In the TC1728 SR[7:0] are connected to interrupt nodes. SR[15:8] are used as DMA channel trigger signals. User’s Manual 11-36 2011-12 DMA, V1.0...
Page 869: Interrupt Request Compressor
SRx. Each interrupt output SR[15:0] can also be activated by writing a 1 to the corresponding bit GINTR.SIDMAx. 1) In the TC1728 SR[7:0] are connected to interrupt nodes. SR[15:8] are used as DMA channel trigger signals. User’s Manual 11-37 2011-12...
Page 870: Pattern Detection
TC1728 Direct Memory Access Controller (DMA) CHICRmn CHICRmn INTP SIDMA0 ≥1 MEm DMA Channel To SR1 Interrupt Interrupts (8) & Output Pattern Det. To SR14 Interrupts (8) TRLINP To SR1 MEm Transaction Lost Interrupts (1) To SR14 MEmINP To SR1...
Page 871 TC1728 Direct Memory Access Controller (DMA) As the compare match patterns are stored in the Move Engine 0 (register ME0PR), its compare patterns are used for all DMA channels that are assigned to Move Engine 0 (all DMA channels of the DMA Sub-Block 0.
Page 872: Pattern Compare Logic
TC1728 Direct Memory Access Controller (DMA) 11.2.13.1 Pattern Compare Logic Read move data and compare match patterns are compared on a bit-wise level. The logic as shown in Figure 11-22 is implemented in each COMP block of Figure 11-23, Figure...
Page 873: Pattern Detection For 8-Bit Data Width
TC1728 Direct Memory Access Controller (DMA) 11.2.13.2 Pattern Detection for 8-bit Data Width When 8-bit channel data width is selected (CHCRmn.CHDW = 00 ), the pattern detection logic is configured as shown in Figure 11-23. Three compare match configurations are possible.
Page 874: Pattern Detection For 16-Bit Data Width
TC1728 Direct Memory Access Controller (DMA) 11.2.13.3 Pattern Detection for 16-bit Data Width When 16-bit channel data width is selected (CHCRmn.CHDW = 01 ) the pattern detection logic can be configured as shown in Figure 11-24. Three compare match configurations are possible.
Page 875 TC1728 Direct Memory Access Controller (DMA) mode that combines the pattern search capability for aligned and unaligned 16-bit data searches. MExPR ADRCRxz CHCRxz CHSRxz PAT0[3] PAT0[2] PAT0[1] PAT0[0] INCS PATSEL Mask COMP Pattern Detected ≥1 Mask COMP & Mask COMP...
Page 876: Pattern Detection For 32-Bit Data Width
TC1728 Direct Memory Access Controller (DMA) 11.2.13.4 Pattern Detection for 32-bit Data Width When 32-bit channel data width is selected (CHCRmn.CHDW = 10 ) the pattern detection logic is configured as shown in Figure 11-25. Three compare match configurations are possible.
Page 877: Access Protection
The two parameters (SIZE, SLICE) of the four address range extensions of a move engine are numbered by index “n” (n = 0-3). In the TC1728 the number “a” is defined in the followign way: User’s Manual...
Page 878 Note: The definition of the fixed address ranges x and the assignment of each sub-range to one of the fixed address ranges is product-specific. The definitions of the address ranges for the DMA controller as implemented in the TC1728 are defined Page 11-112.
Page 879 TC1728 Direct Memory Access Controller (DMA) Fixed Address Range a a-1 Fixed Address Variable Address Assigned for AENx x = 0-31 Programmable Address Range Extension SIZE = 111 Fixed Address Variable Address SIZE = 110 Fixed Address Variable Address SIZE = 101...
Page 880: Dma Module Registers
Table 11-29. All DMA kernel register names described in this section are also referenced in other parts of the TC1728 User’s Manual by the module name prefix “DMA_”. The registers are numbered by one index to indicate the related DMA Sub-Block and one index to indicate the related DMA channel: Index “m”...
Page 881 TC1728 Direct Memory Access Controller (DMA) Table 11-8 Registers Overview - DMA Control Registers Short Description Offset Access Mode Reset Description Name Addr. Class Read Write DMA_CLC DMA Clock Control U, SV SV, E Page 11-122 Register Reserved DMA_ID DMA Module...
Page 882 TC1728 Direct Memory Access Controller (DMA) Table 11-8 Registers Overview - DMA Control Registers Short Description Offset Access Mode Reset Description Name Addr. Class Read Write DMA_ME1 DMA Move Engine 1 U, SV SV Page 11-81 Pattern Register DMA_ DMA Move Engine 0...
Page 883 TC1728 Direct Memory Access Controller (DMA) Table 11-8 Registers Overview - DMA Control Registers Short Description Offset Access Mode Reset Description Name Addr. Class Read Write DMA_CHC DMA Channel mn (n x 20 U, SV SV Page 11-86 Control Register...
Page 884 TC1728 Direct Memory Access Controller (DMA) Table 11-8 Registers Overview - DMA Control Registers Short Description Offset Access Mode Reset Description Name Addr. Class Read Write Reserved DMA_ DMA MLI0 Service U, SV SV Page 11-124 MLI0SRC3 Request Control Reg.
Page 885 TC1728 Direct Memory Access Controller (DMA) 2) Write access mode to DMA_SHADRmn is controlled by the register bit DMA_ADRCRmn.SHWEN. DMA_ADRCRmn.SHWEN=´0´ -> Access Mode Write DMA_SHADRmn DMA_ADRCRmn.SHWEN=´1´ -> Access Mode Write for DMA_SHADRmn is SV. Note: Register bits marked “w” in the following register description are virtual registers and do not contain flip-flops.
Page 886: System Registers
TC1728 Direct Memory Access Controller (DMA) 11.3.1 System Registers DMA Module Identification Register. DMA_ID Module Identification Register (008 Reset Value: 001A C0XX MOD_NUMBER MOD_TYPE MOD_REV Field Bits Type Description MOD_REV [7:0] Module Revision Number This bit field defines the module revision number.
Page 887 TC1728 Direct Memory Access Controller (DMA) DMA_OCDSR DMA OCDS Register (064 Reset Value: 0000 0000 BCHS1 BTRC1 BCHS0 BTRC0 Field Bits Type Description BTRC0 [1:0] Break Trigger Condition In Sub-Block 0 This bit field determines the transition type for the transaction request bit TRSR.CH0n that leads to a...
Page 888 TC1728 Direct Memory Access Controller (DMA) Field Bits Type Description BRL0 Break On Request Lost in Sub-Block 0 This bit field determines whether a BREAK signal is generated for DMA Sub-Block 0 when at least one of its eight transaction lost interrupts becomes active.
Page 889 TC1728 Direct Memory Access Controller (DMA) The Suspend Mode Register contains bits for each DMA channel that make it possible to enable/disable its Soft-suspend Mode capability and that indicate its suspend status. DMA_SUSPMR DMA Suspend Mode Register (068 Reset Value: 0000 0000...
Page 890 TC1728 Direct Memory Access Controller (DMA) Field Bits Type Description SUSEN1n Suspend Enable for DMA Channel 1n (n = 0-7) This bit enables the soft suspend capability individually for each DMA channel 1n. DMA channel 1n is disabled for Soft-suspend Mode.
Page 891 DMA interrupt output line SRx will be activated. Reading this bit returns a 0 [31:16] Reserved Read as 0; should be written with 0. Note: In the TC1728, SR[7:0] are connected to interrupt nodes. SR[15:8] are used as DMA channel request inputs (Page 11-102). User’s Manual...
Page 892: General Control/Status Registers
TC1728 Direct Memory Access Controller (DMA) 11.3.2 General Control/Status Registers The bits in the Channel Reset Request Register are used to reset DMA channel mn. DMA_CHRSTR DMA Channel Reset Request Register (010 Reset Value: 0000 0000 Field Bits Type Description...
Page 893 TC1728 Direct Memory Access Controller (DMA) The bits in the Transaction Request State Register indicates which DMA channel is processing a request, and which DMA channel has hardware transaction requests enabled. DMA_TRSR DMA Transaction Request State Register (014 Reset Value: 0000 0000...
Page 894 TC1728 Direct Memory Access Controller (DMA) Field Bits Type Description HTRE1n 24+n Hardware Transaction Request Enable State of DMA (n = 0-7) Channel 1n Hardware transaction request for DMA Channel 1n is disabled. An input DMA request will not trigger the channel 1n.
Page 895 TC1728 Direct Memory Access Controller (DMA) The bits in the Software Transaction Request Register are used to generate a DMA transaction request by software. DMA_STREQ DMA Software Transaction Request Register (018 Reset Value: 0000 0000 Field Bits Type Description SCH0n...
Page 896 TC1728 Direct Memory Access Controller (DMA) The bits in the Hardware Transaction Request Register enable or disable DMA hardware requests. DMA_HTREQ DMA Hardware Transaction Request Register (01C Reset Value: 0000 0000 Field Bits Type Description ECH0n Enable Hardware Transfer Request...
Page 897 TC1728 Direct Memory Access Controller (DMA) Table 11-9 Conditions to Set/Reset the Bits TRSR.HTREmn (cont’d) HTREQ.ECHmn HTREQ.DCHmn Transaction Finishes Modification of for Channel mn TRSR.HTREmn Reset Reset 1) In Single Mode only. In Continuous Mode, the end of a transaction has no impact.
Page 898 TC1728 Direct Memory Access Controller (DMA) The Enable Error Register describes how the DMA controller reacts to errors. It enables the interrupts for the loss of a transaction request or Move Engine errors. DMA_EER DMA Enable Error Register (020 Reset Value: 0000 0000...
Page 899 0001 SR1 selected for Move Engine 0 interrupt … … 1111 SR15 selected for Move Engine 0 interrupt Note: In the TC1728, SR[7:0] are connected to interrupt nodes. SR[15:8] are used as DMA channel request inputs (Page 11-102). User’s Manual...
Page 900 0001 SR1 selected for Move Engine 1 interrupt … … 1111 SR15 selected for Move Engine 1 interrupt Note: In the TC1728, SR[7:0] are connected to interrupt nodes. SR[15:8] are used as DMA channel request inputs (Page 11-102). TRLINP [31:28] rw...
Page 901 TC1728 Direct Memory Access Controller (DMA) The Error Status Register indicates if the DMA controller could not answer to a request because the previous request was not terminated (see Section 11.2.4.4). It indicates also the FPI Bus accesses that have been terminated with errors.
Page 902 TC1728 Direct Memory Access Controller (DMA) Field Bits Type Description ME0SER Move Engine 0 Source Error This bit is set whenever a Move Engine 0 error occurred during a source (read) move of a DMA transfer, or a request could not been serviced due to the access protection.
Page 903 TC1728 Direct Memory Access Controller (DMA) Field Bits Type Description LMBER LMB Error This bit is set whenever a move that has been started by the DMA/MLI LMB master interface leads to an error on the LMB Bus. No error occurred.
Page 904 TC1728 Direct Memory Access Controller (DMA) The Clear Error contains bits that make it possible to clear the Transaction Request Lost flags or the Move Engine error flags. DMA_CLRE DMA Clear Error Register (028 Reset Value: 0000 0000 FPIE MLI0...
Page 905 TC1728 Direct Memory Access Controller (DMA) Field Bits Type Description CME1DER Clear Move Engine 1 Destination Error No action Clear destination error flag ERRSR.ME1DER. CFPIER Clear FPI Error No action Clear error flag ERRSR.FPIER. CLMBER Clear LMB Error No action Clear error flag ERRSR.LMBER.
Page 906 TC1728 Direct Memory Access Controller (DMA) The Interrupt Status Register indicates if CHSRmn.TCOUNT matches with CHCRmn.IRDV, or if CHSRmn.TCOUNT has been decremented (depending on CHICRmn.INTCT[0]),or if a pattern has been detected. These conditions can also generate an interrupt if enabled (see...
Page 907 TC1728 Direct Memory Access Controller (DMA) Field Bits Type Description IPM0n 16+n Pattern Detection from Channel 0n (n = 0-7) This bit indicates that a pattern has been detected for channel 0n while the pattern detection has been enabled. This bit (and ICH0n) is reset by software when writing a 1 to INTCR.CICH0n or by a channel...
Page 908 TC1728 Direct Memory Access Controller (DMA) The Wrap Status Register gives information about the channels that did a wrap-around on their source or destination buffer(s). This condition can also lead to an interrupt if it is enabled. DMA_WRPSR DMA Wrap Status Register...
Page 909 TC1728 Direct Memory Access Controller (DMA) Field Bits Type Description WRPD1n 24+n Wrap Destination Buffer for Channel 1n (n = 0-7) These bits indicate which channels have done a wrap-around of their destination buffer(s). No wrap-around occurred for channel 1n.
Page 910 TC1728 Direct Memory Access Controller (DMA) The bits in the Interrupt Clear Register make it possible to reset the channel interrupt flags and the wrap buffer interrupt flags for DMA Channels mn. DMA_INTCR DMA Interrupt Clear Register (058 Reset Value: 0000 0000...
Page 911: Move Engine Registers
TC1728 Direct Memory Access Controller (DMA) Field Bits Type Description CWRP1n 24+n Clear Wrap Buffer Interrupt for DMA Channel 1n (n = 0-7) These bits make it possible to reset the wrap source buffer interrupt flag WRPSR.WRPS1n and the wrap destination buffer interrupt flag WRPSR.WRPD1n...
Page 912 [7:5] Read Buffer Trace for FPI Bus Interface This bit field contains trace information from the buffer in the FPI Bus Interface. In the TC1728 it indicates the source of a bus access to the FPI Bus. Default value. DMA Move Engine 0...
Page 913 TC1728 Direct Memory Access Controller (DMA) The Move Engine 0 Read Register indicates the value that has just been read by Move Engine 0. The value in this register is compared to the bits in register ME0PR according to the bit fields CHCRmn.PATSEL.
Page 914 TC1728 Direct Memory Access Controller (DMA) Field Bits Type Description PAT00, [7:0], Pattern for Move Engine 0 PAT01, [15:8], Determines up to four 8-bit compare patterns/mask PAT02, [23:16], patterns to be processed by the pattern detection PAT03 [31:24] logic in Move Engine 0. Depending on the pattern detection configuration (CHCR0n.PATSEL) and...
Page 915 If AENx = 0 for a read/write move to address range x, the read/write move is not executed and a source/destination Move Engine interrupt is generated. Note: See Table 11-13 Page 11-112 for the TC1728-specific address range definition. User’s Manual 11-83 2011-12 DMA, V1.0...
Page 916 TC1728 Direct Memory Access Controller (DMA) The DMA Move Engine 0 Access Range Register determines number and size of the sub-ranges for address range extension n (n = 0-3). See also Figure 11-26 for bit field definitions. DMA_ME0ARR DMA Move Engine 0 Access Range Register...
Page 917 3. SIZE3 [31:29] Address Size 3 SIZE3 determines the sub-range size within address range extension 3. Note: See Section 11.4.2 Page 11-112 for the TC1728-specific address range and address range extension definitions. User’s Manual 11-85 2011-12 DMA, V1.0...
Page 918: Channel Control/Status Registers
TC1728 Direct Memory Access Controller (DMA) 11.3.4 Channel Control/Status Registers The Channel Control Register for DMA channel mn contains its configuration and its control bits and bit fields. DMA_CHCR0x (x = 0-7) DMA Channel 0x Control Register (084 +x*20 Reset Value: 0000 0000...
Page 919 TC1728 Direct Memory Access Controller (DMA) Field Bits Type Description PRSEL [15:12] Peripheral Request Select This bit field controls the hardware request input multiplexer of DMA channel mn (see Figure 11-6 Page 11-11). 0000 Input CHmn_REQI0 selected 0001 Input CHmn_REQI1 selected...
Page 920 TC1728 Direct Memory Access Controller (DMA) Field Bits Type Description CHMODE Channel Operation Mode CHMODE determines the reset condition for control bit TRSR.HTREmn of DMA channel mn. Single Mode operation is selected for DMA channel mn. After a transaction, DMA channel mn is disabled for further hardware requests (TRSR.HTREmn is reset by hardware)
Page 921 TC1728 Direct Memory Access Controller (DMA) Field Bits Type Description CHPRIO Channel Priority CHPRIO determines the priority of DMA channel n for the Move Engine minternal channel arbitration. This priority is used for the case when multiple channels of Move Engine m are triggered in parallel.
Page 922 TC1728 Direct Memory Access Controller (DMA) The Channel Status Register contains the current transfer count and a pattern detection compare result. DMA_CHSR0x (x = 0-7) DMA Channel 0x Status Register (080 +x*20 Reset Value: 0000 0000 DMA_CHSR1x (x = 0-7)
Page 923 TC1728 Direct Memory Access Controller (DMA) The Channel Interrupt Control Register controls the interrupts generation. DMA_CHICR0x (x = 0-7) DMA Channel 0x Interrupt Control Register (088 +x*20 Reset Value: 0000 0000 DMA_CHICR1x (x = 0-7) DMA Channel 1x Interrupt Control Register...
Page 924 SR1 selected for channel mx wrap buffer interrupt … … 1111 SR15 selected for channel mx wrap buffer interrupt Note: In the TC1728, SR[7:0] are connected to interrupt nodes. SR[15:8] are used as DMA channel request inputs (Page 11-102). INTP [11:8]...
Page 925 TC1728 Direct Memory Access Controller (DMA) The Address Control Register controls how source and destination addresses are updated after a DMA move. Furthermore, it determines whether or not a source or destination address register update is shadowed. DMA_ADRCR0x (x = 0-7)
Page 926 TC1728 Direct Memory Access Controller (DMA) Field Bits Type Description INCS Increment of Source Address This bit determines whether the address offset as selected by SMF will be added to or subtracted from the source address after each DMA move. The source...
Page 927 TC1728 Direct Memory Access Controller (DMA) Field Bits Type Description CBLS [11:8] Circular Buffer Length Source This bit field determines which part of the 32-bit source address register remains unchanged and is not updated after a DMA move operation (see also Section 11.2.4.7).
Page 928 TC1728 Direct Memory Access Controller (DMA) Field Bits Type Description SHCT [17:16] rw Shadow Control This bit field determines whether an address is transferred into the shadow address register when writing to source or destination address register. Shadow address register not used. Source and...
Page 929 TC1728 Direct Memory Access Controller (DMA) Table 11-10 shows the offset values that are added or subtracted to/from a source or destination address register after a DMA move. Bit field SMF and bit INCS determine the offset value for the source address. Bit field DMF and bit INCD determine the offset value for the destination address.
Page 930: Channel Address Registers
TC1728 Direct Memory Access Controller (DMA) 11.3.5 Channel Address Registers The Source Address Register contains the 32-bit source address. If a DMA channel mn is active, SADRmn is updated continuously (if programmed) and shows the actual source address that is used for read moves within DMA transfers.
Page 931 TC1728 Direct Memory Access Controller (DMA) The Destination Address Register contains the 32-bit destination address. If a DMA channel is active, DADRmn is updated continuously (if programmed) and shows the actual destination address that is used for write moves within DMA transfers.
Page 932 TC1728 Direct Memory Access Controller (DMA) The Shadow Address Register holds the shadowed source or destination address before it is written into the source or destination address register. SHADRmn can be read only. DMA_SHADR0x (x = 0-7) DMA Channel 0x Shadow Address Register...
Page 933: Dma Module Implementation
TC1728 Direct Memory Access Controller (DMA) 11.4 DMA Module Implementation This section describes the TC1728 DMA module interfaces with the clock control, interrupt control, and address decoding. Figure 11-28 shows the TC1728-specific implementation details and interconnections of the DMA module. The DMA module is supplied with a separate clock control, address decoding, interrupt control, and the request input wiring matrix.
Page 934: Dma Request Wiring Matrix
TC1728 Direct Memory Access Controller (DMA) 11.4.1 DMA Request Wiring Matrix The DMA request input lines of each DMA channel within DMA Sub-Block 0 and DMA Sub-Block 1 are connected to request output lines from the peripheral modules according to Table 11-11.
Page 935 TC1728 Direct Memory Access Controller (DMA) Table 11-11 DMA Request Assignment for DMA Sub-Block 0 (cont’d) DMA Request Line DMA Requesting Unit Selected by Channel GPTA_TRIG01 GPTA CHCR01.PRSEL = 1001 GPTA_TRIG11 GPTA CHCR01.PRSEL = 1010 TINT0SRC ERAY CHCR01.PRSEL = 1011 Reserved CHCR01.PRSEL = 1100...
Page 936 TC1728 Direct Memory Access Controller (DMA) Table 11-11 DMA Request Assignment for DMA Sub-Block 0 (cont’d) DMA Request Line DMA Requesting Unit Selected by Channel MLI0_SR7 MLI0 CHCR03.PRSEL = 0111 STMIRQ0 CHCR03.PRSEL = 1000 GPTA_TRIG03 GPTA CHCR03.PRSEL = 1001 GPTA_TRIG13 GPTA CHCR03.PRSEL = 1010...
Page 937 TC1728 Direct Memory Access Controller (DMA) Table 11-11 DMA Request Assignment for DMA Sub-Block 0 (cont’d) DMA Request Line DMA Requesting Unit Selected by Channel ASC1_TDR ASC1 CHCR05.PRSEL = 0101 MSC0_SR3 MSC0 CHCR05.PRSEL = 0110 MLI0_SR5 MLI0 CHCR05.PRSEL = 0111 STMIRQ0 CHCR05.PRSEL = 1000...
Page 938 TC1728 Direct Memory Access Controller (DMA) Table 11-11 DMA Request Assignment for DMA Sub-Block 0 (cont’d) DMA Request Line DMA Requesting Unit Selected by Channel ADC_SR07 CHCR07.PRSEL = 0011 SSC1_RDR SSC1 CHCR07.PRSEL = 0100 ASC1_RDR ASC1 CHCR07.PRSEL = 0101 CAN_INT_O1 MultiCAN CHCR07.PRSEL = 0110...
Page 939 TC1728 Direct Memory Access Controller (DMA) Table 11-12 DMA Request Assignment for DMA Sub-Block 1 (cont’d) DMA Request Line DMA Requesting Unit Selected by Channel GPTA_TRIG00 GPTA CHCR00.PRSEL = 1001 GPTA_TRIG10 GPTA CHCR00.PRSEL = 1010 INT1SRC ERAY CHCR00.PRSEL = 1011...
Page 940 TC1728 Direct Memory Access Controller (DMA) Table 11-12 DMA Request Assignment for DMA Sub-Block 1 (cont’d) DMA Request Line DMA Requesting Unit Selected by Channel MLI0_SR6 MLI0 CHCR02.PRSEL = 0111 STMIRQ0 CHCR02.PRSEL = 1000 GPTA_TRIG02 GPTA CHCR02.PRSEL = 1001 GPTA_TRIG12 GPTA CHCR02.PRSEL = 1010...
Page 941 TC1728 Direct Memory Access Controller (DMA) Table 11-12 DMA Request Assignment for DMA Sub-Block 1 (cont’d) DMA Request Line DMA Requesting Unit Selected by Channel ASC0_TDR ASC0 CHCR04.PRSEL = 0101 MSC0_SR2 MSC0 CHCR04.PRSEL = 0110 MLI0_SR4 MLI0 CHCR04.PRSEL = 0111 STMIRQ0 CHCR04.PRSEL = 1000...
Page 942 TC1728 Direct Memory Access Controller (DMA) Table 11-12 DMA Request Assignment for DMA Sub-Block 1 (cont’d) DMA Request Line DMA Requesting Unit Selected by Channel ADC_SR06 CHCR06.PRSEL = 0011 SSC0_RDR SSC0 CHCR06.PRSEL = 0100 ASC0_RDR ASC0 CHCR06.PRSEL = 0101 CAN_INT_O0 MultiCAN CHCR06.PRSEL = 0110...
Page 943 TC1728 Direct Memory Access Controller (DMA) 1) GPTA_TRIG signals are per default level sensitive signals while a DMA channel is activated with every active request signal cycle. The DMA internal positive edge detection will generate the channel request with the rising edge of the GPTA_TRIG signal, if selected.
Page 944: Access Protection Assignment
DMA access protection as described on Page 11-45 requires the assignment of 32 fixed address range. Table 11-13 shows this address range assignment as implemented in the TC1728 (see also: Page 11-82, Page 11-82). Table 11-13 DMA Access Protection Address Ranges...
Page 945 TC1728 Direct Memory Access Controller (DMA) Table 11-13 DMA Access Protection Address Ranges (cont’d) Access Protection Range Related Module(s) No. n Enable Bit in Selected Address Range MEmAENR AEN19 F010 C000 - F010 C0FF MLI0 Module, F01E 0000 - F01E 7FFF...
Page 946 TC1728 Direct Memory Access Controller (DMA) In the TC1728, four internal memory areas (SPRAM and LDRAM, PRAM, and OVRAM) are protected by an address range verification in addition to the access enable bits. The address range verification is based on the bit fields SIZEx and SLIZEx (x = 3-0), which are located in the registers MEmARR (m = 1-0).
Page 947 TC1728 Direct Memory Access Controller (DMA) SIZE0 and SLICE0 bit fields: PMI sub-range access protection Bit fields SIZE0 and SLICE0 for the PMI memory sub-range access protection (24 KB SPRAM) as shown in Table 11-14. The PMI memory is protected with a min. granularity of 0.5 KB up to the end address...
Page 948 TC1728 Direct Memory Access Controller (DMA) Table 11-14 PMI Address Protection Sub-Range Definition (cont’d) SIZE0 Sub-Ranges SLICE0 Selected Address Range 2 sub-ranges of XXXX0 xxxx 0000 - xxxx 7FFF 32 Kbytes XXXX1 xxxx 8000 - xxxx FFFF 64 Kbytes XXXXX...
Page 949 TC1728 Direct Memory Access Controller (DMA) Table 11-15 OVRAM Address Protection Sub-Range Definition (cont’d) SIZE1 Sub-Ranges SLICE1 Selected Address Range 8 sub-ranges of XX000 xxx0 0000 - xxx0 1FFF 8 Kbytes XX001 xxx0 2000 - xxx0 3FFF … … XX111...
Page 950 TC1728 Direct Memory Access Controller (DMA) Table 11-16 DMI Address Protection Sub-Range Defintions (cont’d) SIZE2 Sub-Ranges SLICE2 Selected Address Range 16 sub-ranges of X0000 xxx0 0000 - xxx0 1FFF 8 Kbytes X0001 xxx0 2000 - xxx0 3FFF … … X1111...
Page 951 TC1728 Direct Memory Access Controller (DMA) Table 11-17 PCP PRAM Address Protection Sub-Range DefintionScheme SIZE3 Sub-Ranges SLICE3 Selected Address Range 32 sub-ranges of 00000 F005 0000 - F005 07FF 2 Kbytes 00001 F005 0800 - F005 0FFF … … 11111...
Page 952: Implementation-Specific Dma Registers
TC1728 Direct Memory Access Controller (DMA) 11.4.3 Implementation-specific DMA Registers The DMA controller as implemented in the TC1728 contains the following additional registers: • DMA clock control register • Service request control registers for DMA controller interrupts (DMA_SRCx) • Service request control registers for MLI module interrupts (DMA_MLI0ySRC.x) Figure 11-29 provides an overview of these registers.
Page 953 TC1728 Direct Memory Access Controller (DMA) The DMA controller module contains in total 12 interrupt request nodes with its interrupt service request control registers: • Eight interrupt requests SR[7:0] = INT_O[7:0] from the DMA controller; upper eight interrupt requests of the DMA controller INT_O[15:8] are used ad DMA channel trigger inputs •...
Page 954: Clock Control Register
TC1728 Direct Memory Access Controller (DMA) 11.4.3.1 Clock Control Register The Clock Control Register controls the DMA module internal clock signal. This clock is also used for the MLI modules as a common clock that can be individually divided for the MLI modules.
Page 955: Dma Interrupt Registers
Direct Memory Access Controller (DMA) 11.4.3.2 DMA Interrupt Registers In the TC1728, the lower eight DMA controller interrupts SR[7:0] are connected to service request control registers. The upper eight DMA controller interrupt outputs SR[15:8] are used as DMA channel request inputs (Page 11-102).
Page 956: Mli Interrupt Registers
TC1728 Direct Memory Access Controller (DMA) 11.4.3.3 MLI Interrupt Registers The Service Request Control Registers of the MLI module is located inside the DMA address area, because the MLI module does not have its own FPI Bus interface. The MLI module shares one FPI Bus slave interface with the DMA controller.
Page 957: Address Map
TC1728 Direct Memory Access Controller (DMA) 11.4.4 Address Map The DMA controller register block address map is shown in Figure 11-31. It shows how the different register blocks are arranged and adds the absolute address information. DMA Service Request F000 3 EF0...
Page 958: Memory Checker Module
TC1728 Direct Memory Access Controller (DMA) 11.5 Memory Checker Module The Memory Checker Module (MCHK) includes two parallel Cyclic Redundancy Checkers (CRCs) that can be used to check the data consistency of two memories in parallel. Each CRC block contains two algorithm engines: 1.
Page 959: Ethernet Crc-32 Endianness
TC1728 Direct Memory Access Controller (DMA) MCHKIR: memory checker input data bits MCHKRR: memory checker result data bits & AND result bits with polynomial bits in MCHKPOR XOR all bits MCHK_structure Figure 11-32 Implementation of the Memory Checker algorithm 11.5.1.1 Ethernet CRC-32 Endianness In order to comply with the Ethernet CRC-32 standard the endianness of the input word needs to be big endian.
Page 960: Memory Checker Module Registers
TC1728 Direct Memory Access Controller (DMA) 11.5.2 Memory Checker Module Registers This section describes the kernel registers of the Memory Checker module. MCHK Register Overview Module Register Memory Checker Other Registers Registers MCHK_WR MCHK_ID MCHK_IR0 MCHK_RR0 mchk_reg _its MCHK_CRCR0 MCHK_IR1...
Page 961: Memory Checker Module Control Registers
TC1728 Direct Memory Access Controller (DMA) Table 11-19 Registers Overview - Memory Checker Module Control Registers Short Name Description Offset Access Mode Reset Description Addr. Class Read Write MCHK_WR Memory Checker U, SV U, SV Page 11-132 Write Register MCHK_CRC...
Page 962 TC1728 Direct Memory Access Controller (DMA) Field Bits Type Description MOD_TYPE [15:8] Module Type The bit field is set to C0 which defines the module as a 32-bit module. MOD_NUMBE [31:16] Module Number Value This bit field defines a module identification number.
Page 963 TC1728 Direct Memory Access Controller (DMA) A Memory Checker Input Register is used during write moves of a memory checker related DMA transaction as data destination with its fixed register address. If the DMA moves to register, for exampleMCHK_IR0 are 8-bit or 16-bit wide, the unused register bits of the 32-bit MCHKIN0 value are taken as 0s for the current result calculation.
Page 964 DMA controller via the Bus Switch of the DMA controller (see Figure 11-14) does not request the two FPI buses of the TC1728, SPB and DMA, because it is near the MLI modules address ranges. MCHK_WR Memory Checker Write Register...
Page 965 TC1728 Direct Memory Access Controller (DMA) Field Bits Type Description MCHKCRC [31:0] Memory Checker CRC This bit field contains the working CRC32 ethernet polynomial checksum. The stored value is inverted and reflected prior to a read. Therefore if the register is written with all 1’s then the output will be all 0’s.
Page 966: Flexible Crc Engine (Fce)
This document describes the Flexible CRC Engine (FCE) module. The FCE provides a parallel implementation of one or more Cyclic Redundancy Code (CRC) algorithms. The current FCE version for the TC1728 microcontroller implements the IEEE 802.3 ethernet CRC32 and the Castagnoli CRC32C polynomials. FCE’s generic structure enables it to be extended with multiple CRC polynomials.
Page 967: Related Documentation
TC1728 Flexible CRC Engine (FCE) 12.1 Related documentation Input documents • [D1] A painless guide to CRC Error Detection Algorithms, Ross N. Williams • [D2] Autosar R3.1 Rev 0001, Specification of CRC Routines V3.0.2 • [D3] 32-Bit Cyclic Redundancy Codes for Internet Applications, Philip Koopman,...
Page 968: Fce Features
TC1728 Flexible CRC Engine (FCE) 12.2 FCE Features The FCE provides the following features: • Architecture supports up to 4 different CRC polynomials. Current FCE version implements: – IEEE 802.3 CRC32 ethernet polynomial: 0x82608EDB (crc kernel 0) – CRC32C Castagnoli polynomial: 0x8F6E37A0 (crc kernel 1) •...
Page 969: Operational Overview
TC1728 Flexible CRC Engine (FCE) 12.3 Operational overview The FCE is a standard FPI slave module. The FCE is fully synchronous with the FPI bus and runs with a 1:1 clock ratio. It connects to the FPI peripheral bus of a micro-controller.
Page 970 TC1728 Flexible CRC Engine (FCE) Interrupt Bus (PCP or TriCore) FPI Bus FPI Slave only interface FPI Bus Peripheral Interface SMIF signal groups SMIF SMIF SMIF SMIF CRC32C CRC32 IEEE 802.3 Castagnoli Alternate CRC Alternate CRC Ethernet polynomial 2 polynomial 3...
Page 971: Fce Functional Description
TC1728 Flexible CRC Engine (FCE) 12.4 FCE Functional Description Generic CRC Kernel Architecture EINIT Input Register (IR) Config Register (CFG) Byte Reflect Length Register (LENGTH) CFG.REFIN mux2->1 IR_STEP1 CRC Register (CRC) NEXT_CRC=F(IR,CRC) mux2->1 CRC WR access decode NEXT_CRC CRC Register...
Page 972 TC1728 Flexible CRC Engine (FCE) • [4] input data reflected: indicates if each byte of the input parallel data is reflected before being used to compute the CRC • [4] result data reflected: indicates if the final CRC value is reflected or not •...
Page 973 TC1728 Flexible CRC Engine (FCE) CRC operation Software must first ensure that the CRC kernel is properly configured, especially the initial CRC register value written via the CRC register. If the software whishes to use the automatic signature check at the end of a message, the LENGTH register and CHECK registers must be configured with respectively the length (as number of 32-bit words) of the message and the expected signature (CHECK).
Page 974 TC1728 Flexible CRC Engine (FCE) CRC Configuration Register Interrupt generation control [0] Interrupt Control CMI: Enables CRC Mismatch Interrupt [1] Interrupt Control CEI: Enables Configuration Error Interrupt [2] Interrupt Control LEI: Enables Length Error Interrupt [2] Interrupt Control BEI: Enables Bus Error Interrupt...
Page 975 TC1728 Flexible CRC Engine (FCE) Register Protection and Monitoring methods Register Monitoring: applied to CFG and CHECK registers Because CFG and CHECK registers are critical to the CRC operation, some mechanisms to detect and log transient errors are provided. Early detection of transient failures enables to improve the failure detection time and asses the severity of the failure.
Page 976 TC1728 Flexible CRC Engine (FCE) Register Access Protection: applies to LENGTH and CHECK registers In order to reduce the probability of a mis-configuration of the CHECK and LENGTH registers (in the case the automatic check is used), the write access to the CHECK and...
Page 977 TC1728 Flexible CRC Engine (FCE) FCE interrupts Each FCE crc kernel provides one internal interrupt source. The interrupt lines from each crc kernel are ored together to be sent to the FCE interrupt control block that implements the standard interrupt node logic and register. When multiple crc kernels are present within a FCE, the interrupt lines from each crc kernel are ored together to provide a single interrupt source to the interrupt control block.
Page 978: Interfaces Of The Fce Module
TC1728 Flexible CRC Engine (FCE) 12.5 Interfaces of the FCE Module The FCE module implements its own interrupt node, therefore implements an interface to the TriCore and PCP interrupt controllers. For protection purposes it uses the EINIT information to control the configuration of critical resources. The EINIT protection is described in the register chapter.
Page 979: Fce Module Registers
TC1728 Flexible CRC Engine (FCE) 12.6 FCE Module Registers Figure 12-8 Table 12-3 show all registers associated with a FCE crc-kernel. All FCE kernel register names are described in this section. They should get the prefix “FCE_” when used in the context of a product specification.
Page 980 TC1728 Flexible CRC Engine (FCE) FPI Base Address FCE Address Map for FCE @ FCE_FPI System Registers Address Space @ FCE_FPI + 32+ 3 CRC Kernel 0 Address Space (m = 0 ) @ FCE_FPI + 32+ 3 CRC Kernel 1 Address...
Page 981 TC1728 Flexible CRC Engine (FCE) Table 12-3 Registers Overview - CRC Kernel Registers Short Description Offset Access Mode Reset Descriptio Name Addr. Class n See Read Write STSm CRC Status Register + m*20 U, SV U, SV Page 12-24 LENGTHm CRC Length Register...
Page 982: System Registers
TC1728 Flexible CRC Engine (FCE) 12.6.1 System Registers FCE Module Clock Control Register. This register is global to FCE and not part of a crc kernel. FCE does not implement a fractional divider, the FCE kernel (when enabled) always runs with the peripheral bus clock.
Page 983 TC1728 Flexible CRC Engine (FCE) Field Bits Type Description EDIS Sleep Mode Enable Control Used for module Sleep Mode control. Sleep Mode request is regarded. Module is enabled to go into Sleep Mode. Sleep Mode request is disregarded: Sleep Mode cannot be entered on a request.
Page 984 TC1728 Flexible CRC Engine (FCE) Field Bits Type Description SRPN [7:0] Service Request Priority Number Service request is never serviced Service request is on lowest priority Service request is on highest priority Type of Service Control CPU service is initiated...
Page 985 TC1728 Flexible CRC Engine (FCE) FCE_ID Module Identification Register Reset Value: 008A C001 MOD_NUMBER MOD_TYPE MOD_REV Field Bits Type Description MOD_REV [7:0] Module Revision Number This bit field defines the module revision number. The value of a module revision starts with 01 (first revision).
Page 986: Crc Kernel Control/Status Registers
TC1728 Flexible CRC Engine (FCE) 12.6.2 CRC Kernel Control/Status Registers IRm (m = 0-1) Input Register m + m*20 Reset Value: 0000 0000 Field Bits Type Description [31:0] Input Register This bit field holds the 32-bit data to be computed A write to IRm triggers the CRC kernel to update the message checksum according to the IR contents and to the current CRC register contents.
Page 987 TC1728 Flexible CRC Engine (FCE) CFGm (m = 0-1) CRC Configuration Register m + m*20 Reset Value: 0000 0700 CCE FEI CEI CMI Field Bits Type Description CRC Mismatch Interrupt CRC Mismatch Interrupt is disabled CRC Mismatch Interrupt is enabled...
Page 988 TC1728 Flexible CRC Engine (FCE) Field Bits Type Description CRC Check Comparison CRC check comparison at the end of a message is disabled CRC check comparison at the end of a message is enabled REFIN IR Byte Wise Reflection IR Byte Wise Reflection is disabled...
Page 989 TC1728 Flexible CRC Engine (FCE) STSm (m = 0-1) CRC Status Register m + m*20 Reset Value: 0000 0000 FEF LEF CEF CMF Field Bits Type Description CRC Mismatch Flag This bit is set per hardware only. To clear this bit, software must write a 1 to this bit field location.
Page 990 TC1728 Flexible CRC Engine (FCE) Field Bits Type Description [31:4] Reserved Read as 0; should be written with 0. LENGTHm (m = 0-1) CRC Length Register m + m*20 Reset Value: 0000 0000 reserved LENGTH Field Bits Type Description LENGTH...
Page 991 TC1728 Flexible CRC Engine (FCE) CRCm (m = 0-1) CRC Register m + m*20 Reset Value: 0000 0000 Field Bits Type Description [31:0] CRC Register This register enables to directly access the internal CRC register User’s Manual 12-26 V1.0, 2011-12...
Page 992 TC1728 Flexible CRC Engine (FCE) CTRm (m = 0-1) CRC Test Register m + m*20 Reset Value: 0000 0000 Field Bits Type Description Force CRC Mismatch Forces the CRC compare logic to issue an error regardless of the CHECK and CRC values. The...
Page 993: Programming Guide
TC1728 Flexible CRC Engine (FCE) 12.7 Programming Guide This section provides some guidelines showing how the FCE configuration features can be mapped to the AUTOSAR API for CRC32 routines. uint32 Crc_CalculateCRC32 ( uint32 Crc_InitializeCRC32 ( const uint8 * Crc_DataPtr, bool Crc_Refin,...
Page 994 TC1728 Flexible CRC Engine (FCE) Crc_CalculateCRC32 (Crc_DataPtr, Crc_Lenght, Crc_StartValue32) // implements FCE_CalculateCRC32(…) If ( Crc_Lenght % 4 != 0 ) { // Return with Error Length = Crc_Length / 4 FCE_SetCRC32Length( Length ); FCE_SetCRC32Init( Crc_StartValue32 ); For ( i = 0; i < Count; i++ ) { FCE_CRC32Add( (unit32)Crc_DataPtr[4*i] );...
Page 995 TC1728 Flexible CRC Engine (FCE) Crc_CalculateCRC32 (Crc_DataPtr, Crc_Lenght, Crc_StartValue32) // Save current CRC context lenght_save = FCE_CRC32Read(LENGTH); check_save = FCE_CRC32Read(CHECK); crc_save = FCE_CRC32Read(CRC); FCE_CalculateCRC32(…) STS = FCE_CRC32Read(STS) If ( sts.cmf == 1 ) { // There was a CRC mismatch // Restore CRC context FCE_SetCRC32Length( length_save );...
Page 996: Properties Of Crc Code
TC1728 Flexible CRC Engine (FCE) 12.8 Properties of CRC code Hamming Distance The Hamming distance defines the error detection capability of a CRC polynomial. A cyclic code with a Hamming Distance of D can detect all D-1 bit errors. Table 12-4 “Hamming Distance as a function of message length (bits)”...
Page 997: Revision History
TC1728 Flexible CRC Engine (FCE) 12.9 Revision history Table 12-5 Revision history Date Description Name Version 1.6 -> version 1.7 02.12.2009 - Changed CLC reset value to 0x3 A. Vilela Version 1.5 -> version 1.6 09.09.2009 - Updated Module ID to 0x008A_C001 A.
Page 998: Interrupt System
Interrupt System Interrupt System The TC1728 interrupt system provides a flexible and time-efficient means of processing interrupts. This chapter describes the interrupt system for the TC1728. Topics covered include the architecture of the interrupt system, interrupt system configuration, and the interrupt operations of the TC1728 peripherals and Central Processing Unit (CPU).
Page 999 8 SRNs MSC0 2 SRN 2 SRN Cerberus CC6061 8 SRNs 4 SRN 1 SRN GPT120 6 SRNs GPT121 6 SRNs 1 SRN tc1728 _int_system Figure 13-1 Block Diagram of the TC1728 Interrupt System User’s Manual 13-2 V1.0, 2011-12 Interrupt, V1.4...
Page 1000: Service Request Nodes
Some peripheral units of the TC1728 have multiple SRNs. 13.2.1 Service Request Control Registers All Service Request Control Registers in the TC1728 have the same format. In general, these registers contain: • Enable/disable information •...

Infineon Technologies TC1728 User Manual

1 Introduction

2 CPU Subsystem

3 System Control Unit (SCU)

4 On-Chip System Buses and Bus Bridges

5 Program Memory Unit (PMU)

Data Access Overlay (OVC)

Bootrom Content

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Summary of Contents for Infineon Technologies TC1728