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generate compare match interrupts because the compare match interrupts are
automatically disabled after a STM reset operation (CMPxEN = 0). Therefore, before
enabling a compare match interrupt after a STM reset operation, the CMPxIR flags
should be cleared by software (writing register STM_ISSR with CMPxIRR set).
Otherwise, undesired compare match interrupt events are triggered. Details about DMA
connections of STMIR0 and STMIR1 are given in
14.3
STM Registers
This section describes the STM registers of the STM. The STM registers can be divided
into four types, as shown in
STM Registers Overview
Module Control
Register
STM_CLC
STM_ID
Figure 14-4 STM Registers
In TC1728 all registers are readable is suspend mode. The complete and detailed
address map of the STM module with its registers is shown in
Page
14-21.
Table 14-2
Registers Address Space
Module
Base Address
STM
F000 0200
User's Manual
STM, V1.6
Figure
14-4.
Timer/Capture
Registers
STM_TIM0
STM_TIM1
STM_TIM2
STM_TIM3
STM_TIM4
STM_TIM5
STM_TIM6
STM_CAP
End Address
F000 02FF
H
14-7
System Timer (STM)
Table 14-4
on
Page
Compare
Registers
STM_CMP0
STM_CMP1
STM_CMCON
H
TC1728
14-21.
Interrupt
Registers
STM_ICR
STM_ISRR
STM_SRC0
STM_SRC1
MCA06188_mod
Table 14-5
on
Note
-
V1.0, 2011-12
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