Infineon Technologies TC1728 User Manual page 1268

The Interrupt Control Register ICR holds the interrupt enable bits and interrupt pointers
of all four MSC interrupts.
ICR
Interrupt Control Register
31 30 29 28
15 14 13 12
RDIE RDIP
rw rw
Field Bits
EDIP [1:0]
EDIE [3:2]
User's Manual
MSC, V1.37 2009-05
27 26 25 24
11 10 9 8
TFIE 0 TFIP
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Type Description
rw Data Frame Interrupt Node Pointer
EDIP selects the service request output line SRn
(n = 0-3) for the data frame interrupt.
00 Service request output SR0 selected
B
01 Service request output SR1 selected
B
10 Service request output SR2 selected
B
11 Service request output SR3 selected
B
rw Data Frame Interrupt Enable
This bit field determines the enable conditions for the
data frame interrupt.
00 Interrupt generation disabled
B
01 An interrupt is generated when the last data bit
B
has been shifted out.
10 An interrupt is generated when the first data bit
B
has been shifted out, but only if DSC.NDBL is
not equal 00000
SRL bit must be shifted out for the first data bit
shifted interrupt to become active.
11 Interrupt generation disabled
B
Micro Second Channel (MSC)
(40 )
H
23 22 21
0
r
7 6 5
ECIE 0 ECIP
rw r rw
. This means, at least one
B
19-49
TC1728
Reset Value: 0000 0000
20 19 18 17
4 3 2 1
EDIE EDIP
rw
V1.0, 2011-12
H
16
0
rw