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Field
Bits
IE
8
PIPN
[23:16] rh
CARBCYC
[25:24] rw
CONECYC
26
0
[15:9],
[31:27]
User's Manual
Interrupt, V1.4
Type Description
rwh
Global Interrupt Enable Bit
The interrupt enable bit globally enables the CPU
service request system. Whether or not a service
request is delivered to the CPU depends on the
individual Service Request Enable Bits (SRE) in the
SRNs, and the current state of the CPU.
IE is automatically updated by hardware on entry and
exit of an Interrupt Service Routine (ISR).
IE is cleared to 0 when an interrupt is taken, and is
restored to the previous value when the ISR executes
an RFE instruction to terminate itself.
IE can also be updated through the execution of the
ENABLE, DISABLE, MTCR, and BISR instructions.
0
Interrupt system is globally disabled
1
Interrupt system is globally enabled
Pending Interrupt Priority Number
PIPN is a read-only bit field that is updated by the ICU
at the end of each interrupt arbitration process. It
indicates the priority number of the pending service
request. PIPN is set to 0 when no request is pending,
and at the beginning of each new arbitration process.
00
No valid pending request
H
YY
A request with priority YY
H
Number of Arbitration Cycles
CARBCYC controls the number of arbitration cycles
used to determine the request with the highest priority.
00
4 arbitration cycles (default)
B
01
3 arbitration cycles
B
10
2 arbitration cycles
B
11
1 arbitration cycle
B
rw
Number of Clocks per Arbitration Cycle Control
The CONECYC bit determines the number of system
clocks per arbitration cycle. For the TC1728 this bit
can be set to 1 (for SPB frequencies up to the max SPB
frequency as defined in the Data Sheet).
0
2 clocks per arbitration cycle (default)
1
1 clock per arbitration cycle
r
Reserved
Read as 0; should be written with 0.
13-9
TC1728
Interrupt System
is pending
H
V1.0, 2011-12
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