Infineon Technologies TC1728 User Manual page 1271

The Interrupt Status Register ISR holds the interrupt status flags that indicate an
interrupt occurrence in downstream and upstream channels.
ISR
Interrupt Status Register
31 30 29 28
15 14 13 12
Field Bits
DEDI 0
DECI 1
DTFI 2
User's Manual
MSC, V1.37 2009-05
(44
27 26 25 24
11 10 9 8
0
r
Type Description
rh Data Frame Interrupt Flag
This flag is always set by hardware when a
downstream channel data frame interrupt is
generated. DEDI can be set or cleared by software
when writing to register ISC with the appropriate bits
ISC.SDEDI or ISC.CDEDI set.
rh Command Frame Interrupt Flag
This flag is always set by hardware when a
downstream channel command frame interrupt is
generated, whether or not it is enabled. DECI can be
set or cleared by software when writing to register ISC
with the appropriate bits SDECI or CDECI set.
rh Time Frame Interrupt Flag
This flag is always set by hardware when a
downstream channel time frame interrupt is
generated, whether or not it is enabled. DTFI can be
set or cleared by software when writing to register ISC
with the appropriate bits SDTFI or CDTFI set.
19-52
Micro Second Channel (MSC)
) Reset Value: 0000 0000
H
23 22 21
0
r
7 6 5
TC1728
20 19 18 17
4 3 2 1
URDI DTFI DECI DEDI
rh rh rh
V1.0, 2011-12
H
16
0
rh