Infineon Technologies TC1728 User Manual page 396

Field Bits
TAG [27:24] rwh
OPC [31:28] rwh
1) In the TC1728, aborted accesses to a 0 wait state SPB slave may also increment ERRCNT when the slave
generates an error acknowledge.
Table 4-14 FPI Bus Read/Write Error Indication
RD WR
0 0
0 1
1 0
1 1
SBCU_EADD
SBCU Error Address Capture Register (024
31
Field Bits
FPIADR [31:0]
User's Manual
Buses, V1.9
Type Description
FPI Bus Master Tag Number Signals
This bit field indicates the FPI Bus master TAG
number (definitions see
FPI Bus Operation Code Signals
The FPI Bus operation codes are defined in
Table
FPI Bus Cycle
FPI Bus error occurred at the read transfer of a read-modify-write
transfer.
FPI Bus error occurred at a read cycle of a single transfer.
FPI Bus error occurred at a write cycle of a single transfer or at the
write cycle of a read-modify-write transfer.
Does not occur.
Type Description
rwh Captured FPI Bus Address
This bit field holds the 32-bit FPI Bus address that has
been captured at an FPI Bus error. Note that if multiple
bus errors occurred, only the address of the first bus
error is captured.
On-Chip System Buses and Bus Bridges
Table
4-11.
)
H
FPIADR
rwh
4-51
TC1728
4-15).
Reset Value: 0000 0000
V1.0, 2011-12
H
0