Infineon Technologies TC1728 User Manual page 1091

Field Bits
SEC_EN 0
0 [31:1]
Please see "Error Correction Code (ECC)" on Page 15-18
regarding the use of this register.
Note: This register is ENDINIT protected, in addition the register cannot be accessed
unless the "secwen_i" input is asserted. When "secwen_i" is not asserted
accesses to
User's Manual
BMU, V2.6
Type Description
rw Single error correction enable
0
B
1
B
r reserved
returns '0' if read; should be written with '0'.
MIECON2 will generate an FPI error acknowledge.
Single bit error correction for BMURAM
disabled
Single bit error correction for BMURAM
enabled
15-47
TC1728
Bus Monitor Unit (BMU)
for more information
V1.0, 2011-12