Infineon Technologies TC1728 User Manual page 743

Field Bits
PPS [15:9]
PPE 8
CS [7:6]
EIE 5
User's Manual
PCP, V2.09
Type Description
rw PRAM Partition Size
0 Default, only allowed with PPE = 0
D
1 CSA contains 3 context save regions
D
...
CSA contains 1 + 2 × 127 context save regions
127
D
Note: The actual size of the CSA (in words) is given by
the formula (2
number of registers in the selected Context
Model.
If PPE = 1 and the PCP attempts to perform a
data write to PRAM addresses below the CSA,
an error condition has occurred.
This setting also controls the maximum channel
number (MCN) used in system. The maximum
channel number is MCN = 2
greater than MCN, an error condition has
occurred.
For example, setting PPS to n = 3 will give a
CSA containing 7 context save regions. As
channel 0 cannot be used and MCN = 6,
channels 1 to 6 are allowed.
rw PRAM Partitioning Enable
0 PRAM is not partitioned
B
1 PRAM is partitioned
B
Note: When partitioned, the PRAM is divided into two
areas (CSA and remainder). A PCP error will be
generated on an inappropriate action in either
region (PCP write operation with a target
address in the CSA, or context restore from
outside the CSA).
rw Context Size Selection
00 Use Full Context for all channels
B
01 Use Small Context for all channels
B
10 Use Minimum Context for all channels
B
11 Reserved
B
rw Endinit Enable
0 PCP_CS is not Endinit protected.
B
1 PCP_CS is Endinit protected.
B
10-71
Peripheral Control Processor (PCP)
× ×
n + 1) m, where m is the
TC1728
×
n. If the SRPN is
V1.0, 2011-12