Bus Monitor Unit Overview - Infineon Technologies TC1728 User Manual

15.3.2

Bus Monitor Unit Overview

The BMU is a standard FPI slave module that implements a FPI slave interface and a
Bus Peripheral Interface (BPI) compliant with the FPI bus architecture. The BMU is not
FPI master capable. The BMU is fully synchronous with the FPI bus clock and runs with
a 1:1 clock ratio. It does not implement a fractional divider
Peripherals
Peripherals
Peripherals
(SPB Slaves)
(FPI Slaves)
(FPI Slaves)
Figure 15-2 BMU overview
In addition to the standard FPI connectivity, the BMU also receives the individual
peripheral select signals decoded by the address decoders. The granularity of each
select line is not a peripheral but a FPI region that may include several peripherals.
Each decoded region provides a FPI_ACK[1:0] signal that indicates the completion
status of each individual data phase. The FPI_ACK[1:0] of the FPI regions listed in
Table 15-4 "Identification of FPI Regions" on Page 15-22
determine if write transactions have been normally terminated or not.
User's Manual
BMU, V2.6
System Peripheral Bus (SPB)
Monitoring
Port
Entry = {Addr, Data, Master ID }
System
Control Unit
(SCU)
Application
f
SPB
Reset
Address
Decoder
bmu_cs
Slave
Interface
Transaction FIFO
Bus Monitor Unit
(BMU)
15-6
TC1728
Bus Monitor Unit (BMU)
are required by the BMU to
V1.0, 2011-12