Compare Match Interrupt Control - Infineon Technologies TC1728 User Manual

A compare operation with MSIZE not equal 0 always implies that the compared value as
stored in the CMP register is right-extended with zeros. This means that in the example
of Figure 14-2, the compare register content STM_CMP0[17:0] plus nine zero bits right-
extended is compared with STM[27:0] with STM[8:0] = 000
STM_CMP1, STM[14:0] with STM[5:0] = 00
six zero bits right-extended.
14.2.3

Compare Match Interrupt Control

The compare match interrupt control logic is shown in
register has its compare match interrupt request flag (STM_ICR.CMPxIR) that is set by
hardware on a compare match event. The interrupt request flags can be set
(STM_ISSR.CMPxIRS) or cleared (STM_ISSR.CMPxIRR) by software. Note that setting
STM_ICR.CMPxIR by writing a 1 into STM_ISSR.CMPxIRS does not generate an
interrupt at STMIRx. The compare match interrupts from CMP0 and CMP1 can be further
directed by STM_ICR.CMPxOS to either output signal STMIR0 or STMIR1. The STMIR0
and STMIR1 outputs are each connected to interrupt service request control registers,
STM_SRC0 and STM_SCR1, respectively.
Compare Match
Event from CMP 0
Register Set
STM_ICR Register
CMP1
Compare Match
Event from CMP 1
Register Set
Figure 14-3 STM Interrupt Control
The compare match interrupt flags STM_ICR.CMPxIR are immediately set after an STM
reset operation, caused by a compare match event with the reset values of the STM and
the compare registers STM_CMPx. This setting of the CMPxIR flags does not directly
User's Manual
STM, V1.6
CMP1 CMP1 CMP0
OS IR EN OS
STM_ISRR Reg.
CMP1
IRS
Set
Clear
are compared with STM_CMP1[8:0] plus
H
Figure
CMP0 CMP0
IR EN
Clear
Set
CMP1 CMP0 CMP0
IRR IRS IRR
14-6
System Timer (STM)
. In case of register
H
14-3. Each STM_CMPx
0
1
³1
STMIR0
³1
STMIR1
0
1
MCA06187_mod
V1.0, 2011-12
TC1728