Compare Register Operation - Infineon Technologies TC1728 User Manual

14.2.2

Compare Register Operation

The content of the 56-bit STM can be compared against the content of two compare
values stored in the STM_CMP0 and STM_CMP1 registers. Service requests can be
generated on a compare match of the STM with the STM_CMP0 or STM_CMP1
registers.
Two parameters are programmable for the compare operation:
1. The width of the relevant bits in registers STM_CMP0/STM_CMP1 (compare width
MSIZEx) that is taken for the compare operation can be programmed from 1 to 32.
2. The first bit location in the 56-bit STM that is taken for the compare operation can be
programmed from 0 to 24.
These programming capabilities make compare functionality very flexible. It even makes
it possible to detect bit transitions of a single bit n (n = 0 to 24) within the 56-bit STM by
setting MSIZE = 0 and MSTART = n.
STM_CMP0
MSIZEx = 0-31
MSTARTx = 0-24
55 47
STM_CMP1
Figure 14-2 Compare Mode Operation
Figure 14-2 shows an example of the compare operation. In this example the following
parameters are programmed:
• MSIZE0 = 10001
• MSIZE1 = 00111
User's Manual
STM, V1.6
31 23 15
Compare Register 0
39 31 23
56-bit System Timer
31 23
Compare Register 1
= 17 ; MSTART0 = 01010
B D
= 7 ; MSTART1 = 00111
B D
MSIZE0
7
Equal ?
15 7
MSTART1
MSTART0
Equal ?
15 7
MSIZE1
= 9
B D
= 6
B D
14-5
TC1728
System Timer (STM)
Compare Match
Event with STM_CMP0
Register
Compare Match
Event with STM_CMP1
Register
MCA06186_mod
V1.0, 2011-12