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15.4.2
Handling of FPI corner cases
There are specific situations that lead to exceptions with respect to the correct
termination of a FPI write transaction, like: master aborts, slave retries, time-out,... The
flag FPI_STATUS indicates if the write data phase has been normally completed
(FPI_STATUS = 1) or not (FPI_STATUS = 0). In the case of an error there is no
additional information that defines the nature of the error.
A Data Phase is completed when the target BPI interface issues a FPI_RDY=1; the
signal FPI_ACK[1:0] provides additional information about the status of the completion.
The BPI can insert wait states in the FPI bus by delaying the assertion of FPI_RDY. The
following situations lead to the detection of an error condition indicating that a write data
phase has been either aborted by the master or not accepted by the slave:
•
The FPI Master FPI_ABORT_N is asserted during the data phase wait states or
coincides with the FPI_RDY assertion by the BPI. If this happens during a burst all
subsequent data phases are aborted.
•
The BPI issues FPI_RDY=1 together with FPI_ACK=2'b11 (ERR).
•
The BPI issues FPI_RDY=1 together with FPI_ACK=2'b10 (RTY).
•
In the occurrence of a timeout, FPI_TOUT is issued by the Bus Control Unit during
one clock cycle and the selected slave must terminate the data transfer with an error
condition (FPI_RDY=1 with FPI_ACK=2'b11) in the following cycle. Therefore the
FPI_TOUT does not need to be handled by BMU.
Please refer to the FPI specification version V4.2, 2003-11 chapter 6: FPI Bus
Termination conditions for a detailed overview.
User's Manual
BMU, V2.6
15-11
TC1728
Bus Monitor Unit (BMU)
V1.0, 2011-12
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