Clock Control - Infineon Technologies TC1728 User Manual

20.3.2

Clock Control

The CAN module timer clock
derived from the asynchronous, higher precision clock
f
to generate used for bit timing calculation, The frequency of
CAN
CAN nodes. The register file operate with the module control clock
"Module Clock Generation" on Page
f
The output clock
CAN
th clock pulse is taken. The suspend signal (coming as acknowledge from the MultiCAN
module in response to a OCDS suspend request) freezes or resets the Fractional
Divider.
Clock
f
SYS
Control
Register
Figure 20-8 MultiCAN Clock Generation
Table 20-2 indicates the minimum operating frequencies in MHz for
for a baud rate of 1 Mbit/s for the active CAN nodes. If a lower baud rate is desired, the
values can be scaled linearly (e.g. for a maximum of 500 kbit/s, 50% of the indicated
value are required).
The values imply that the CPU (or DMA) executes maximum accesses to the MultiCAN
module. The values may contain rounding effects.
User's Manual
MultiCAN, V2.24
Controller Area Network Controller (MultiCAN)
f of the functional blocks of the MultiCAN module is
CAN
20-115.
of the Fractional Divider is based on the clock
f
A3
f
A2
Clock
f
A1 Select
f
A0
f
CLC
f
. The Fractional Divider is used
A
f f
Fractional
A CAN
Divider
f
CLC
20-17
TC1728
f
is identical for all
CAN
f
. See also
CLC
f
, but only every n-
A
Module Kernel
Baud Rate
Prescalers
Register
File
MCA06265_b
f that are required
A
V1.0, 2011-12