Ssc0/Ssc1/Ssc2/Ssc3 Module Implementation; Module Identification Registers; Interfaces Of The Ssc Modules - Infineon Technologies TC1728 User Manual

18.3

SSC0/SSC1/SSC2/SSC3 Module Implementation

This section describes SSC0/SSC1/SSC2/SSC3 module interfaces with the clock
control, port connections, interrupt control, and address decoding.
18.3.1

Module Identification Registers

The reset values of the SSCx_ID module identification registers are 0000 4512
18.3.2

Interfaces of the SSC Modules

Figure 18-16 and
interconnections of the SSC0/SSC1/SSC2/SSC3 modules.
Each of the SSC modules is supplied with a separate clock control, interrupt control, and
address decoding logic. Two interrupt outputs can be used to generate DMA requests.
The SSC0/SSC1/SSC2/SSC3 I/O lines are connected to Port 1, Port 2, Port 3, Port 5,
Port 8, and Port 10.
User's Manual
SSC, V1.41 2010-06
Figure 18-17 show the TC1798-specific implementation details and
Synchronous Serial Interface (SSC)
18-43
TC1728
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V1.0, 2011-12