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Field
Bits
SDEDI
16
SDECI
17
SDTFI
18
SURDI
19
SDP
20
SCP
21
SDDIS
22
0
[15:7],
[31:23]
Note: When the ISC register is written with both bits (set and reset bit) for a specific
interrupt flag, the clear operation takes place and the set operation is ignored.
User's Manual
MSC, V1.37 2009-05
Type Description
w
Set DEDI Flag
0
No operation
B
1
Bit ISR.DEDI is set.
B
w
Set DECI Flag
0
No operation
B
1
Bit ISR.DECI is set.
B
w
Set DTFI Flag
0
No operation
B
1
Bit ISR.DTFI is set.
B
w
Set URDI Flag
0
No operation
B
1
Bit ISR.URDI is set.
B
w
Set DP Bit
0
No effect
B
1
Bit DSC.DP is set.
B
w
Set CP Flag
0
No operation
B
1
Bit DSC.CP is set.
B
w
Set DSDIS Flag
0
No operation
B
1
Bit DSC.DSDIS is set.
B
r
Reserved
Read as 0; should be written with 0.
19-55
Micro Second Channel (MSC)
TC1728
V1.0, 2011-12
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