Infineon Technologies TC1728 User Manual page 1228

32-bit single-chip microcontroller
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Data Frames
A data frame has two active phase parts, SRL active phase and SRH active phase. The
number of bits that are transmitted can be programmed separately for each of these two
phases. Bit field DSC.NDBL determines the number of SRL bits that are transmitted
during the SRL active phase and DSC.NDBH determines the number of SRH bits that
are transmitted during the SRH active phase.
SRL and SRH active phases can start with a low-level selection bit when enabled by bits
DSC.ENSELL or DSC.ENSELH.
During the SRL active phase of a data frame, the enable output signal ENL becomes
active and during the SRH active phase of a data frame, the enable output signal ENH
becomes active. The enable output signal ENC remains inactive.
The length of the data frame's passive phase is variable and is defined by bit field
DSC.PPD. It can be within a range of 2 ×
Figure 19-6
assumes that the FCL clock is only generated during the active phase of the
data frame (OCR.CLKCTRL = 0).
Table
19-2,
Table
parameters that determine the layout of the data frame.
ENL
ENH
Selection Bit
FCL
SO
0
1) Interrupt generation possible
Figure 19-6 Data Frame Layout
User's Manual
MSC, V1.37 2009-05
19-3, and
Table 19-4
1)
SRL.0
SRL.n
Length defined by
DSC.NDBL
SRL Active Phase
Active Phase
Micro Second Channel (MSC)
up to 31 ×
t
FCL
show the definitions of the five data frame
Data Frame
Selection Bit
t
FCL
0
SRH.0
Length defined by
DSC.NDBH
SRH Active Phase
19-9
t
. The diagram shown in
FCL
SRL.m
Length defined
by DSC.PPD
Passive Phase
MCT06232
V1.0, 2011-12
TC1728
1)

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