Infineon Technologies TC1784 Manuals

Manuals and User Guides for Infineon Technologies TC1784. We have 1 Infineon Technologies TC1784 manual available for free PDF download: User Manual

Infineon Technologies TC1784 User Manual (2350 pages)

32-Bit Single-Chip Microcontroller

Brand: Infineon Technologies | Category: Microcontrollers | Size: 15 MB

Table of Contents
7
1 Introduction

40
- About this Document
  40
- Related Documentations
  40
- Text Conventions
  40
- Reserved, Undefined, and Unimplemented Terminology
  42
- Register Access Modes
  42
- Abbreviations and Acronyms
  43
- System Architecture of the TC1784
  46
- TC1784 Block Diagram
  47
- System Features
  48
- CPU Cores of the TC1784
  49
- High-Performance 32-Bit CPU
  49
- High-Performance 32-Bit Peripheral Control Processor
  50
- On-Chip System Units
  51
- Flexible Interrupt System
  51
- Direct Memory Access Controller
  51
- System Timer
  52
- System Control Unit
  55
- Clock Generation Unit
  55
- Features of the Watchdog Timer
  55
- Reset Operation
  55
- External Interface
  56
- Die Temperature Measurement
  56
- General Purpose I/O Ports and Peripheral I/O Lines
  56
- Program Memory Unit (PMU)
  57
- Boot ROM
  58
- Overlay RAM and Data Acquisition
  58
- Emulation Memory Interface
  58
- Tuning Protection
  58
- Program and Data Flash
  58
- Data Access Overlay
  62
- Development Support
  62
- On-Chip Peripheral Units of the TC1784
  64
- Asynchronous/Synchronous Serial Interfaces
  64
- High-Speed Synchronous Serial Interfaces (SSC)
  66
- Micro Second Channel Interface (MSC)
  69
  - Flexray™ Protocol Controller (E-Ray)
    71
  - Micro Link Interface (MLI)
    76
- General Purpose Timer Array (Intro)
  79
- Functionality of GPTA0
  80
- Functionality of LTCA2
  82
- Analog-To-Digital Converters
  83
- ADC Block Diagram
  83
- FADC Short Description
  85
- External Bus Interface
  88
- On-Chip Debug Support (OCDS)
  88
- On-Chip Debug Support
  88
- Real Time Trace
  89
- Calibration Support
  89
- Tool Interfaces
  90
- Self-Test Support
  90
- FAR Support
  90
2 CPU Subsystem

91
- TC1784 Processor Subsystem
  91
- Central Processing Unit Features
  92
- CPU Diagram
  93
- Instruction Fetch Unit
  94
- Execution Unit
  95
- General Purpose Register File
  96
- CPU Implementation-Specific Features
  97
- Context Save Areas
  97
- Program Counter Register - PC
  97
- Interrupt System
  99
- Trap System
  99
- Memory Integrity Error Handling
  100
- Program Side Memories
  100
- Data Side Memories
  102
- Tricore 1.3 Compatibility
  105
- CPU Subsystem Registers
  106
- CPU Core Special Function Registers (CSFR)
  107
- Registers
  109
- CPU General Purpose Registers
  114
- CPU Memory Protection Registers
  117
- FPU Registers
  123
- Registers
  124
- Memory Integrity Registers
  125
- Register Descriptions
  127
- CPU Slave Interface (CPS) Registers
  142
- Register Descriptions
  143
- Core Debug Registers
  146
- Implementation Specific Reset Values
  148
- CPU Instruction Timing
  149
- Integer-Pipeline Instructions
  150
- Simple Arithmetic Instruction Timings
  150
- Multiply Instruction Timings
  154
- Multiply Accumulate (MAC) Instruction Timing
  155
- Control Flow Instruction Timing
  156
- Load-Store Pipeline Instructions
  157
- Address Arithmetic Timing
  157
- Control Flow Instruction Timing
  158
- Load Instruction Timing
  159
- Store Instruction Timing
  160
- Floating Point Pipeline Timing
  161
- Program Memory Interface (PMI)
  162
- PMI Features
  162
- LMB Access Priorities
  163
- Scratchpad RAM
  163
- Instruction Cache
  164
- Program Line Buffer
  165
- PMI Registers
  166
- PMI Register Descriptions
  167
- Data Memory Interface (DMI)
  173
- DMI Features
  173
- LMB Access Priorities
  174
- Local Data RAM (LDRAM)
  174
- Data Cache
  174
- Data Line Buffer
  175
- DMI Trap Generation
  176
- DMI Registers
  178
- DMI Register Descriptions
  179
3 System Control Unit (SCU)

184
- Clock System Overview
  185
- Clock Generation Unit
  187
- Overview
  187
- Oscillator Circuit (OSC)
  188
- Phase-Locked Loop (PLL) Module
  190
- ERAY Phase-Locked Loop (PLL_ERAY) Module
  198
- Clock Control Unit
  206
- External Clock Output
  208
- CGU Registers
  213
- Module Clock Generation
  232
- Clock Control Register CLC
  233
- Reset Operation
  245
- Overview
  245
- Reset Types
  245
- Reset Sources Overview
  246
- Module Reset Behavior
  246
- General Reset Operation
  247
- Reset State Machine
  248
- Reset Counters (RSTCNTA and RSTCNTD)
  248
- De-Assertion of a Reset
  250
- Example1
  250
- Example2
  250
- Example3
  250
- Reset Triggers
  250
- Specific Reset Triggers
  251
- Configurable Reset Triggers
  251
- Debug Specific Behavior
  251
- EEC Reset Specific Behavior
  251
- Reset Controller Registers
  252
- Status Registers
  252
- Configuration Registers
  254
- External Interface
  259
- External Service Requests (Esrx)
  259
- Esrx as Reset Request Trigger
  259
- Esrx as Reset Output
  260
- ESR Registers
  261
- External Request Unit (ERU)
  268
- Introduction
  268
- External Request Select Unit (ERS)
  270
- ERU Pin Connections
  270
- Event Trigger Logic (ETL)
  271
- Connecting Matrix
  273
- Output Gating Unit (OGU)
  275
- ERU Output Connections
  277
- External Request Unit Registers
  279
- Power Management
  294
- Power Management Overview
  294
- Power Management Modes
  295
- Idle Mode
  295
- Sleep Mode
  296
- Power Management Control and Status Register, PMCSR
  296
- Software Boot Support
  299
- Configuration Done with Start-Up
  299
- Start-Up Configuration Options
  299
- Start-Up Registers
  300
- Start-Up Status Register
  300
- ECC Error Handling
  303
- ECC Software Testing Support
  303
- ECC Registers
  304
- Die Temperature Measurement
  310
- Die Temperature Sensor Register
  311
- Watchdog Timer
  313
- Watchdog Timer Overview
  313
- Features of the Watchdog Timer
  313
- The Endinit Function
  314
- Password Access to WDT_CON0
  316
- Modify Access to WDT_CON0
  317
- Access to Endinit-Protected Registers
  318
- Timer Operation
  318
- Timer Modes
  318
- WDT Reset Behavior
  320
- WDT Operation During Power-Saving Modes
  321
- Suspend Mode Support
  322
- Watchdog Timer Registers
  322
- Watchdog Timer Control Register 0
  322
- Watchdog Timer Control Register 1
  322
- Watchdog Timer Status Register
  326
- Emergency Stop Output Control
  329
- Emergency Stop Register
  331
- Interrupt Generation
  333
- Interrupt Control Registers
  334
- NMI Trap Generation
  345
- Trap Control Registers
  346
- Miscellaneous System Control Register
  355
- GPTA Input IN1 Control
  355
- Identification Registers
  357
- SCU Kernel Registers
  362
- SCU Address Area
  368
4 On-Chip System Buses and Bus Bridges

369
- What Is New
  370
- Local Memory Bus
  371
- Overview
  371
- Transaction Types
  371
- Single Transfers
  371
- Block Transfers
  372
- Atomic Transfers
  372
- Address Alignment Rules
  372
- Reaction of a Busy Slave
  372
- LMB Basic Operation
  373
- Local Memory Bus Controller Unit
  374
- Basic Operation
  374
- LMB Bus Arbitration
  374
- LMB Bus Default Master
  375
- LMB Bus Error Handling
  375
  - LMB Bus Control Unit Registers
    376
    
    LMB Bus Control Unit Control Registers
    378
- Local Memory Bus to FPI Bus Interface (LFI Bridge)
  384
- Functional Overview
  384
- LMB to FPI Bridge Control Registers
  386
- LFI Register Description
  387
- System Peripheral Bus
  389
- Overview
  389
- Bus Transaction Types
  391
- Reaction of a Busy Slave
  391
- Address Alignment Rules
  392
- FPI Bus Basic Operations
  392
- FPI Bus Control Unit (SBCU)
  394
- FPI Bus Arbitration
  394
- Arbitration on the System Peripheral Bus
  394
- Starvation Prevention
  396
- FPI Bus Error Handling
  396
- BCU Debug Support
  399
- Address Triggers
  399
- Signal Status Triggers
  400
- Grant Triggers
  401
- Combination of Triggers
  402
- BCU Breakpoint Generation Examples
  402
  - System Bus Control Unit Registers
    405
- SBCU ID Register Description
  407
- SBCU Control Registers Descriptions
  408
- SBCU Error Registers Descriptions
  409
- SBCU OCDS Registers Descriptions
  413
- SBCU Service Request Control Register Description
  426
- On Chip Bus Master TAG Assignments
  427
5 Program Memory Unit (PMU)

428
- Bootrom
  430
- Addressing
  430
- Firmware Program Structure
  430
- Overlay RAM and Data Acquisition
  431
- Internal Overlay Memory
  431
- Online Data Acquisition (OLDA)
  431
- Access Performance
  432
- Overlay Memory Control Register
  432
- Emulation Memory Interface
  434
- PMU ID Register
  435
- Tuning Protection
  436
- Program and Data Flash
  437
- Introduction
  437
- Architectural and Operational Overview
  441
- Sector and
  441
- Data Flash and EEPROM Emulation
  442
- Operational Overview
  444
- Flash Access Control and Performance
  451
- Functional Description
  453
- Address Mapping
  453
- Basic Operating Modes
  455
- Command Sequence Definitions
  455
- Functional Command Description
  458
- Sector, Page and Block Addressing
  467
- Register Addresses and Access Restrictions
  470
- Flash Status Definition
  473
- Flash Configuration Control
  480
- Flash Identification Register
  486
- Error Correction and Margin Control
  487
- Dynamic Error Correction
  487
- Margin Check Control
  488
- Read and Write Protection
  491
- Read Protection
  491
- Write and OTP Protection
  494
- Protection Configuration Indication
  495
- User Configuration Blocks and
  503
- Interrupt, Error and Operation Control
  505
- Interrupt Control
  505
- Trap Control
  505
- Handling Errors During Operation
  506
- Handling Errors During Startup
  511
- Application Hints and Guidelines
  513
- Power Supply and Reset
  516
- Power Supply
  516
- Flash Power Consumption
  516
- Flash Sleep Mode
  516
- Reset Control
  518
6 Data Access Overlay (OVC)

522
- Basic Overlay Control
  522
- Online Data Acquisition (OLDA) and Its Overlay
  525
- Enable Control of Overlay Blocks
  525
- Target and Overlay Memories
  526
- Target Memories
  526
- Internal Overlay Memory
  526
- Emulation Overlay Memory
  527
- External Overlay Memory
  527
- Change of Overlay Parameters and Overlay Start
  527
- Block Priority and Access Performance
  528
- Overlay Control Registers
  528
7 Bootrom Content

543
- Start-Up Mode Selection
  543
- Internal Start
  544
- External Start
  544
- Bootstrap Loading
  545
- Common Procedures for All Bootloaders
  545
- ASC Bootstrap Loader
  546
- CAN Bootstrap Loader
  547
- Alternate Boot Modes
  548
- Header Check in Alternate Boot Modes
  548
- Startup Errors Handling
  551
- Notes and Usage Hints
  552
- Conditions Upon User Code Start
  552
- Rams Handling
  552
- Influencing the Next SSW-Execution
  552
8 Memory Maps

553
- What Is New
  554
- How to Read the Address Maps
  555
- Contents of the Segments
  557
- Address Map of the FPI Bus System
  559
- Segments 0 to 14
  559
- Segment 15
  564
- Address Map of the Local Memory Bus (LMB)
  570
- Memory Module Access Restrictions
  575
- Side Effects from Modules to LDRAM
  576
9 General Purpose I/O Ports and Peripheral I/O Lines (Ports)

577
- Basic Port Operation
  577
- Description Scheme for the Port IO Functions
  578
- Description of the Port Operation
  579
- Port Register Description
  581
- Port Input/Output Control Registers
  584
- Pad Driver Mode Register
  589
- Port Output Register
  592
- Port Output Modification Register
  593
- Emergency Stop Register
  595
- Port Input Register
  596
- Port 0
  597
- Port 0 Configuration
  597
- Port 0 Function Table
  597
- Port 0 Registers
  602
- Port 0 Pad Driver Mode Register and Pad Classes
  603
- Port 0 Emergency Stop Register
  603
- Port 1
  604
- Port 1 Configuration
  604
- Port 1 Function Table
  605
- Port 1 Registers
  610
- Port 1 Output Register
  610
- Port 1 Output Modification Register
  610
- Port 1 Input/Output Control Register 12
  611
- Port 1 Input Register
  611
- Port 1 Pad Driver Mode Register and Pad Classes
  611
- Port 1 Emergency Stop Register
  612
- Port 2
  613
- Port 2 Configuration
  613
- Port 2 Function Table
  613
- Port 2 Registers
  617
- Port 2 Output Register
  617
- Port 2 Output Modification Register
  617
- Port 2 Input Register
  617
- Port 2 Pad Driver Mode Register and Pad Classes
  618
- Port 2 Emergency Stop Register
  618
- Port 3
  619
- Port 3 Configuration
  619
- Port 3 Function Table
  620
- Port 3 Registers
  625
- Port 3 Pad Driver Mode Register and Pad Classes
  626
- Port 3 Emergency Stop Register
  627
- Port 4
  628
- Port 4 Configuration
  628
- Port 4 Function Table
  628
- Port 4 Registers
  629
- Port 4 Output Register
  630
- Port 4 Output Modification Register
  630
- Port 4 Input/Output Control Register X (X = 4, 8 and 12)
  630
- Port 4 Input Register
  630
- Port 4 Emergency Stop Register
  630
- Port 4 Pad Driver Mode Register and Pad Classes
  631
- Port 5
  632
- Port 5 Configuration
  632
- Port 5 Function Table
  633
- Port 5 Registers
  637
- Port 5 Emergency Stop Register
  637
- Port 5 Pad Driver Mode Register and Pad Classes
  638
- Port 6
  639
- Port 6 Registers
  640
- Port 6 Functions
  641
- Port 6 Pad Driver Mode Register
  642
- Port 6 Emergency Stop Register
  642
- Port 7
  643
- Port 7 Registers
  643
- Port 7 Functions
  644
- Port 7 Pad Driver Mode Register
  649
- Port 7 Emergency Stop Register
  649
- Port 8
  650
- Port 8 Registers
  650
- Port 8 Functions
  651
- Port 8 Pad Driver Mode Register
  655
- Port 8 Emergency Stop Register
  655
- Port 9
  656
- Port 9 Registers
  656
- Port 9 Functions
  657
- Port 9 Pad Driver Mode Register
  659
- Port 9 Emergency Stop Register
  659
- Port 10
  660
- Port 10 Registers
  660
- Port 10 Functions
  661
- Port 10 Pad Driver Mode Register
  665
- Port 10 Emergency Stop Register
  665
10 Peripheral Control Processor (PCP)

666
- PCP Feature/Enhancement History List
  666
- Switchable Core Clock Ratio
  667
- Peripheral Control Processor Overview
  667
- High Integrity Operation
  667
- PCP Architecture
  668
- PCP Processor
  669
- PCP Code Memory
  670
- CMEM Protection
  670
- PCP Parameter RAM
  670
- PRAM Protection
  671
- FPI Bus Interface
  671
- PCP Interrupt Control Unit and Service Request Nodes
  671
- PCP Programming Model
  673
- General Purpose Register Set of the PCP
  673
- Register R0
  674
- Registers R1, R2, and R3
  674
- Registers R4 and R5
  674
- Register R6
  675
- Register R7
  676
- Contexts and Context Models
  678
- Context Models
  678
- Context Save Area
  681
- Context Restore Operation for CR6 and CR7
  684
- Context Save Operation for CR6 and CR7
  688
- Initialization of the Contexts
  691
- Context Save Optimization
  691
- Channel Programs
  692
- Channel Restart Mode
  692
- Channel Resume Mode
  693
- PCP Operation
  695
- PCP Initialization
  695
- Channel Invocation and Context Restore Operation
  695
- Channel Exit and Context Save Operation
  696
- Normal Exit
  696
- Error Condition Channel Exit
  697
- Debug Exit
  698
- PCP Interrupt Operation
  699
- Issuing Service Requests to CPU or PCP
  700
- PCP Interrupt Control Unit
  700
- PCP Service Request Nodes
  700
- Issuing PCP Service Requests
  701
- Service Request on EXIT Instruction
  702
- Service Request on Suspension of Interrupt
  702
- Service Request on Error
  703
- Queue Full Operation
  703
- PRAM Protection
  704
- Protection of PRAM against FPI Writes
  706
- Protection of PRAM against Internally Generated PRAM Writes
  706
- Context Save Region Protection
  706
- Protected Channel PRAM Protection
  707
- FPI Interface
  707
- Operation as an FPI Master
  707
- Operation as an FPI Slave
  708
- PCP Error Handling
  709
- PRAM Protection Violation
  709
- Enforced PRAM Partitioning
  709
- Protected Channel PRAM
  710
- FPI Write Window Violation
  710
- Channel Watchdog
  710
- Invalid Opcode
  710
- Instruction Address Error
  711
- Software In-System Test Support
  711
- Memory Integrity Error Detection
  712
- Instruction Set Overview
  713
- DMA Primitives
  713
- Load and Store
  714
- Arithmetic and Logical Instructions
  715
- Bit Manipulation
  717
- Flow Control
  717
- Addressing Modes
  718
- FPI Bus Addressing
  718
- PRAM Addressing
  719
- Bit Addressing
  719
- Flow Control Destination Addressing
  719
- FPI Interface
  721
- Access to the PCP Control Registers from the FPI Bus
  721
- PCP Control Register Protection
  721
- Access to the PRAM from the FPI Bus
  722
- Access to the CMEM from the FPI Bus
  722
- Debugging the PCP
  724
- PCP Registers
  726
- PCP Registers Address Space
  729
- Registers
  730
- PCP Clock Control Register, PCP_CLC
  730
- PCP Module Identification Register, PCP_ID
  731
- PCP Control and Status Register, PCP_CS
  732
- PCP Error/Debug Status Register, PCP_ES
  734
- PCP Interrupt Control Register, PCP_ICR
  736
- PCP Interrupt Threshold Register, PCP_ITR
  739
- PCP Interrupt Configuration Register, PCP_ICON
  740
- PCP Stall Status Register, PCP_SSR
  742
- SIST Mode Access Control Register, PCP_SMACON
  744
- Register Protection Register, PCP_RPROT
  745
- CMEM Protection Register, PCP_CPROT
  746
- PRAM Protection Register, PCP_PPROT
  747
- FPI Write Window Register, PCP_FWWIN
  751
- PCP Service Request Control Registers M, PCP_SRC[1:0]
  752
- PCP Service Request Control Registers M, PCP_SRC[3:2]
  754
- PCP Service Request Control Registers M, PCP_SRC[8:4]
  755
- PCP Service Request Control Registers M, PCP_SRC[11:9]
  756
- PCP Instruction Set Details
  758
- Instruction Codes and Fields
  758
- Conditional Codes
  759
- Instruction Fields
  760
- Counter Operation for COPY Instruction
  763
- Counter Operation for BCOPY Instruction
  764
- Divide and Multiply Instructions
  765
- ADD, 32-Bit Addition
  766
- AND, 32-Bit Logical and
  767
- BCOPY, DMA Operation
  768
- CHKB, Check Bit
  769
- CLR, Clear Bit
  769
- COMP, 32-Bit Compare
  770
- COPY, DMA Instruction
  771
- DEBUG, Debug Instruction
  772
- DINIT, Divide Initialization
  773
- DSTEP, Divide Instruction
  774
- EXIT, Exit Instruction
  775
- INB, Insert Bit
  776
- JC, Jump Conditionally
  777
- JL, Jump Long Unconditional
  778
- LD, Load
  778
- LDL, Load 16-Bit Value
  780
- MINIT, Multiply Initialization
  780
- MOV, Move Register to Register
  781
- Multiply Instructions
  782
- NEG, Negate
  783
- NOP, no Operation
  783
- NOT, Logical NOT
  783
- OR, Logical or
  784
- PRAM Bit Operations
  785
- PRI, Prioritize
  786
- RL, Rotate Left
  787
- RR, Rotate Right
  787
- SET, Set Bit
  788
- SHL, Shift Left
  788
- SHR, Shift Right
  789
- ST, Store
  790
- SUB, 32-Bit Subtract
  791
- XCH, Exchange
  792
- XOR, 32-Bit Logical Exclusive or
  793
- Flag Updates of Instructions
  794
- Instruction Timing
  795
- Instruction Encoding
  799
- Programming of the PCP
  805
- Initial PC of a Channel Program
  805
- Channel Entry Table
  805
- Channel Resume
  806
- Channel Management for Small and Minimum Contexts
  807
- Unused Registers as Global's or Constants
  807
- Dispatch of Low Priority Tasks
  808
- Code Reuse Across Channels (Call and Return)
  808
- Case-Like Code Switches (Computed Go-To)
  809
- Simple DMA Operation
  809
- COPY Instruction
  809
- BCOPY Instruction (Burst Copy)
  810
- PCP Programming Notes and Tips
  811
- Notes on PCP Configuration
  811
- General Purpose Register Use
  811
- Use of Channel Interruption
  813
- Dynamic Interrupt Masking
  813
- Control of Channel Priority (CPPN)
  813
- Implementing Divide Algorithms
  814
- Implementing Multiply Algorithms
  815
- Implementation of the PCP in the TC1784
  817
- PCP Memories
  817
- BCOPY Instruction
  817
- PCP Reset Operation
  818
11 Direct Memory Access Controller (DMA)

819
- What Is New
  819
- DMA Controller Kernel Description
  821
- Features
  822
- Definition of Terms
  823
- DMA Principles
  824
- DMA Channel Functionality
  825
- Shadowed Source or Destination Address
  825
- DMA Channel Request Control
  829
- DMA Channel Operation Modes
  830
- Error Conditions
  834
- Channel Reset Operation
  835
- Transfer Count and Move Count
  836
- Circular Buffer
  838
- Transaction Control Engine
  839
- Bus Switch, Bus Switch Priorities
  840
- DMA Module Priorities on on Chip Busses (FPI Bus, LMB Bus)
  842
- DMA Module: on Chip Bus Access Rights, RMW Support
  843
- DMA Module on Chip Bus Master Interfaces
  843
- DMA Module Bridge Functionality
  845
- On-Chip Debug Capabilities
  846
- Hard-Suspend Mode
  846
- Soft-Suspend Mode
  846
- Break Signal Generation
  847
- Interrupts
  849
- Channel Interrupts
  849
- Transaction Lost Interrupt
  851
- Move Engine Interrupts
  852
- Wrap Buffer Interrupts
  854
- Interrupt Request Compressor
  855
- Pattern Detection
  856
- Pattern Compare Logic
  858
- Pattern Detection for 8-Bit Data Width
  859
- Pattern Detection for 16-Bit Data Width
  860
- Pattern Detection for 32-Bit Data Width
  862
- Access Protection
  863
- DMA Module Registers
  866
- System Registers
  872
- General Control/Status Registers
  878
- Move Engine Registers
  897
- Channel Control/Status Registers
  904
- Channel Address Registers
  916
- DMA Module Implementation
  919
- DMA Request Wiring Matrix
  920
- Access Protection Assignment
  930
- Implementation-Specific DMA Registers
  938
- Clock Control Register
  940
- DMA Interrupt Registers
  941
- MLI Interrupt Registers
  942
- Address Map
  943
- Memory Checker Module
  944
- Functional Description
  944
- Memory Checker Module Registers
  946
- Memory Checker Module Control Registers
  947
12 LMB External Bus Unit

951
- Feature List
  951
- Block Diagram
  951
- EBU Interface Signals
  953
- Address/Data Bus, AD[15:0]
  953
- Address Bus, A[20:16]
  953
- Chip Selects, CS[3:0]
  953
- Read/Write Control Lines, RD, RD/WR
  954
- Address Valid, ADV
  954
- Byte Controls, BC[1:0]
  954
- Wait Input, WAIT
  955
- EBU Reset
  955
- Allocation of Unused Signals as GPIO
  955
- Control of Pad Pull up and Pull down
  956
- External Bus Arbitration
  957
- Arbitration Modes
  958
- No Bus Arbitration Mode
  958
- Sole Master Arbitration Mode
  958
- Start-Up/Boot Process
  959
- Clocking Strategy and Local Clock Generation
  959
- Local Clock Divider
  959
- Standby Mode
  959
- External Busoperation
  960
- External Memory Regions
  961
- Chip Select Control
  964
- Programmable Device Types
  964
- Support for Multiplexed Device Configurations
  964
- Address Comparison
  967
- Access Parameter Selection
  971
- Programming Sequence Locking
  972
- LMB Bus Width Translation
  972
- Address Alignment During Bus Accesses
  973
- LMB Data Buffering
  974
- Standard Access Phases
  974
- Address Phase (AP)
  974
- Address Hold Phase (AH)
  975
- Command Delay Phase (CD)
  976
- Command Phase (CP)
  976
- Data Hold Phase (DH)
  977
- Recovery Phase (RP)
  977
- Asynchronous Read/Write Accesses
  980
- Signal List
  980
- Standard Asynchronous Access Phases
  981
- Programmable Parameters
  981
- Control of ADV & Other Signal Delays During Asynchronous Accesses
  982
- Accesses to Multiplexed Devices
  985
- Interfacing to Nand Flash Devices
  986
- NAND Flash
  986
- Dynamic Command Delay and Wait State Insertion
  991
- External Extension of the Command Phase by WAIT
  991
- EBU Registers
  995
- Clock Control Register, CLC
  998
- Configuration Register, MODCON
  999
- External Boot Configuration Control Register, EXTBOOT
  1001
- Address Select Register, Addrselx
  1002
- Bus Configuration Register, Busrconx
  1004
- Bus Write Configuration Register, Buswconx
  1007
- Bus Read Access Parameter Register, Busrapx
  1009
- Bus Write Access Parameter Register, Buswapx
  1012
- Test/Control Configuration Register, USERCON
  1015
13 Interrupt System

1016
- Overview
  1016
- Service Request Nodes
  1018
- Service Request Control Registers
  1018
- General Service Request Control Register Format
  1018
- Request Set and Clear Bits (SETR, CLRR)
  1020
- Enable Bit (SRE)
  1020
- Service Request Flag (SRR)
  1020
- Type-Of-Service Control (TOS)
  1021
- Service Request Priority Number (SRPN)
  1021
- Interrupt Control Units
  1023
- Interrupt Control Unit (ICU)
  1023
- ICU Interrupt Control Register (ICR)
  1023
- Operation of the Interrupt Control Unit (ICU)
  1025
- PCP Interrupt Control Unit (PICU)
  1026
- Arbitration Process
  1027
- Controlling the Number of Arbitration Cycles
  1027
- Controlling the Duration of Arbitration Cycles
  1028
- Entering an Interrupt Service Routine
  1028
- Exiting an Interrupt Service Routine
  1029
- Interrupt Vector Table
  1030
- Usage of the TC1784 Interrupt System
  1033
- Spanning Interrupt Service Routines Across Vector Entries
  1033
- Configuring Ordinary Interrupt Service Routines
  1034
- Interrupt Priority Groups
  1034
- Splitting Interrupt Service Across Different Priority Levels
  1035
- Using Different Priorities for the same Interrupt Source
  1036
- Interrupt Priority 1
  1037
- Software-Initiated Interrupts
  1037
- External Interrupts
  1037
- Service Request Node Table
  1038
14 System Timer (STM)

1041
- Overview
  1041
- Operation
  1041
  - System Timer (STM)
    1041
- Resolution and Ranges
  1044
- Compare Register Operation
  1045
- Compare Match Interrupt Control
  1046
- STM Registers
  1047
- Clock Control Register
  1049
- Timer/Capture Registers
  1051
- Compare Registers
  1054
- Interrupt Registers
  1057
- STM Module Implementation
  1061
- On-Chip Service Request Connections
  1061
- STM Address Map
  1061
15 On-Chip Debug Support (OCDS)

1063
- Overview
  1063
- OCDS Level 1
  1067
- Tricore CPU OCDS Level 1
  1068
- Basic Concept
  1068
- Debug Event Generation
  1069
- Debug Actions
  1070
- Tricore OCDS Registers
  1070
- SBCU OCDS Level 1
  1071
  - PCP OCDS Level 1
    1071
- Debug Interface (Cerberus)
  1072
- RW Mode
  1072
- Communication Mode
  1073
- Triggered Transfers
  1073
- Multi Core Break Switch
  1073
- JTAG Interface
  1075
- Device Access Port (DAP)
  1075
- DAP Telegram Format
  1075
- DAP Telegram Catalog
  1075
- Cerberus and JTAG Registers
  1076
16 Asynchronous/Synchronous Serial Interface (ASC)

1079
- ASC Kernel Description
  1079
- Overview
  1080
- General Operation
  1081
- Asynchronous Operation
  1082
- Asynchronous Data Frames
  1083
- Asynchronous Transmission
  1085
- Asynchronous Reception
  1085
- RXD/TXD Data Path Selection in Asynchronous Modes
  1086
- Synchronous Operation
  1087
- Synchronous Transmission
  1088
- Synchronous Reception
  1088
- Synchronous Timing
  1089
- Baud Rate Generation
  1090
- Baud Rates in Asynchronous Mode
  1091
- Baud Rates in Synchronous Mode
  1094
- Hardware Error Detection Capabilities
  1095
- Interrupts
  1095
- ASC Kernel Registers
  1097
- Control Registers
  1098
- Data Registers
  1106
- ASC0/ASC1 Module Implementation
  1108
- Interfaces of the ASC Modules
  1108
- ASC0/ASC1 Module Related External Registers
  1110
- Clock Control Register
  1111
- Peripheral Input Select Register
  1113
- Port Control Registers
  1115
- Interrupt Control Registers
  1117
- DMA Requests
  1118
- Address Map
  1119
17 Synchronous Serial Interface (SSC)

1122
- SSC Kernel Description
  1122
- Overview
  1123
- General Operation
  1124
- Operating Mode Selection
  1126
- Full-Duplex Operation
  1127
  - Half-Duplex Operation
    1130
  - Continuous Transfers
    1131
  - Parity Mode
    1132
  - Port Control
    1133
  - Baud Rate Generation
    1135
  - Slave Select Input Operation
    1137
  - Slave Select Output Generation Unit
    1138
  - Error Detection Mechanisms
    1141
  - Queued SSC Mode
    1145
- SSC Kernel Registers
  1148
  - Module Identification Register
    1149
  - Control Registers
    1150
  - Data Registers
    1163
- SSC0/SSC1/SSC2 Module Implementation
  1164
  - Module Identification Registers
    1164
  - Interfaces of the SSC Modules
    1164
  - On-Chip Connections
    1167
  - SSC0/SSC1/SSC2 Module Related External Registers
    1168
    
    Clock Control
    1169
    
    Port Control
    1173
    
    Interrupt Control Registers
    1179
  - Address Map of the SSC Modules
    1180
- Micro Second Channel (MSC)
  1183
18 Micro Second Channel (MSC)

1185
- MSC Kernel Description
  1185
  - Overview
    1185
  - Downstream Channel
    1187
    
    Frame Formats and Definitions
    1188
    
    Shift Register Operation
    1194
    
    Transmission Modes
    1196
    
    Downstream Counter and Enable Signals
    1201
    
    Abort of Frames
    1202
    
    Baud Rate
    1202
  - Upstream Channel
    1203
    
    Data Frames
    1204
    
    Parity Checking
    1204
    
    Data Reception
    1205
    
    Baud Rate
    1207
    
    Spike Filter
    1208
  - I/O Control
    1209
    
    Downstream Channel Output Control
    1209
    
    Upstream Channel
    1212
  - MSC Interrupts
    1213
    
    Data Frame Interrupt
    1214
- Command Frame Interrupt
  1214
- Time Frame Finished Interrupt
  1215
- Receive Data Interrupt
  1216
- Interrupt Request Compressor
  1217
- MSC Kernel Registers
  1218
- Module Identification Register
  1220
- Status and Control Registers
  1221
- Data Registers
  1241
- MSC Module Implementation
  1244
- Interface Connections of the MSC Module
  1244
- MSC0 Module-Related External Registers
  1246
- Clock Control
  1247
- Clock Control Register
  1249
- Fractional Divider Register
  1250
- Port Control
  1251
- Input/Output Function Selection
  1251
- On-Chip Connections
  1253
- EMGSTOPMSC Signal (from SCU)
  1253
- DMA Controller Service Requests
  1253
- Interrupt Control Registers
  1254
- MSC0 Address Map
  1255
19 Controller Area Network Controller (Multican)

1257
- CAN Basics
  1258
- Addressing and Bus Arbitration
  1258
- CAN Frame Formats
  1259
- Data Frames
  1259
- Remote Frames
  1261
- Error Frames
  1263
- The Nominal Bit Time
  1264
  - Error Detection and Error Handling
    1265
- Overview
  1267
- Multican Module
  1268
- Multican Kernel Functional Description
  1270
- Module Structure
  1270
- Clock Control
  1273
- Port Input Control
  1274
- Suspend Mode
  1274
- CAN Node Control
  1276
- Bit Timing Unit
  1277
- Bitstream Processor
  1278
- Error Handling Unit
  1279
- CAN Frame Counter
  1280
- CAN Node Interrupts
  1280
- Message Object List Structure
  1282
- Basics
  1282
- List of Unallocated Elements
  1283
- Connection to the CAN Nodes
  1283
- List Command Panel
  1284
- CAN Node Analysis Features
  1287
- Analyze Mode
  1287
- Loop-Back Mode
  1287
- Bit Timing Analysis
  1288
- Message Acceptance Filtering
  1290
- Receive Acceptance Filtering
  1290
- Transmit Acceptance Filtering
  1291
- Message Postprocessing
  1293
- Message Object Interrupts
  1293
- Pending Messages
  1295
- Message Object Data Handling
  1297
- Frame Reception
  1297
- Frame Transmission
  1300
- Message Object Functionality
  1303
- Standard Message Object
  1303
- Single Data Transfer Mode
  1303
- Single Transmit Trial
  1303
- Message Object FIFO Structure
  1304
- Receive FIFO
  1306
- Transmit FIFO
  1307
- Gateway Mode
  1308
- Foreign Remote Requests
  1310
- Multican Kernel Registers
  1311
- Global Module Registers
  1314
- CAN Node Registers
  1326
- Message Object Registers
  1344
- Multican Module Implementation
  1365
- Interfaces of the Multican Module
  1365
- Multican Module External Registers
  1366
- Module Clock Generation
  1367
- CAN Clock Control Register
  1368
- Port and I/O Line Control
  1370
- Input/Output Function Selection in Ports
  1370
- Node Receive Input Selection
  1370
- DMA Request Outputs
  1371
- Interrupt Control
  1372
- CAN Service Request Control Register
  1374
- Multican Module Register Address Map
  1375
20 Flexray™ Protocol Controller (E-Ray)

1377
- E-Ray Kernel Description
  1377
- Overview
  1378
- Definitions
  1379
- Block Diagram
  1379
- Programmer's Model
  1382
- Register Map
  1382
- E-Ray Kernel Registers
  1384
- Customer Registers
  1392
- Special Registers
  1399
- Service Request Registers
  1413
- Communication Controller Control Registers
  1460
- Communication Controller Status Registers
  1487
- Message Buffer Control Registers
  1510
- Message Buffer Status Registers
  1517
- Identification Registers
  1538
- Input Buffer
  1540
- Output Buffer
  1551
- Functional Description
  1568
- Communication Cycle
  1568
- Static Segment
  1568
- Dynamic Segment
  1569
- Symbol Window
  1569
- Network Idle Time (NIT)
  1569
  - Configuration of Network Idle Time (NIT) Start and Offset Correction Start
    1569
- Communication Modes
  1571
- Clock Synchronization
  1571
- Global Time
  1571
- Local Time
  1571
- Synchronization Process
  1572
- External Clock Synchronization
  1573
- Error Handling
  1574
- Clock Correction Failed Counter
  1574
- Passive to Active Counter
  1575
- HALT Command
  1575
- FREEZE Command
  1575
- Communication Controller States
  1577
- Communication Controller State Diagram
  1577
- DEFAULT_CONFIG State
  1580
  - Monitor_Mode
    1580
  - READY State
    1581
  - WAKEUP State
    1581
  - STARTUP State
    1586
  - Startup Time-Outs
    1589
  - Path of Leading Coldstart Node (Initiating Coldstart)
    1590
  - NORMAL_PASSIVE State
    1592
  - NORMAL_ACTIVE State
    1592
  - HALT State
    1593
  - Network Management
    1594
  - Filtering and Masking
    1594
    
    Channel ID Filtering
    1595
    
    Frame ID Filtering
    1595
    
    Cycle Counter Filtering
    1596
    
    FIFO Filtering
    1597
    
    Dynamic Segment
    1598
    
    Static Segment
    1598
    
    Transmit Buffers
    1598
    
    Transmit Process
    1598
    
    Frame Transmission
    1599
    
    NULL Frame Transmission
    1600
    
    Frame Reception
    1601
    
    Receive Process
    1601
    
    NULL Frame Reception
    1602
- FIFO Function
  1602
  - Description
    1602
  - Configuration of the FIFO
    1603
  - Access to the FIFO
    1604
- Message Handling
  1604
  - Host Access to Message RAM
    1604
  - Minimum F CLC_ERAY
    1615
  - Flexray™ Protocol Controller Access to Message RAM
    1619
- Message RAM
  1621
  - Header Partition
    1622
  - Data Partition
    1625
  - ECC Check
    1626
- Host Handling of Errors
  1629
  - Self-Healing
    1629
  - CLEAR_RAMS Command
    1629
  - Temporary Unlocking of Header Section
    1629
  - Module Service Request
    1631
  - Restrictions
    1634
- Message Buffers with the same Frame ID
  1634
- E-Ray Module Implementation
  1635
- Interconnections of the E-Ray Module
  1635
- Input/Output Function Selection
  1636
  - Port Control and Connections
    1636
- E-Ray Connections with DMA
  1638
- On-Chip Connections
  1638
- E-Ray Connections with the External Request Unit of SCU
  1639
- E-Ray Connections with the ECC Error Handling Unit of SCU
  1639
- E-Ray Connections with the External Clock Output of SCU
  1639
- Clock Control Register
  1640
- Interrupt Registers
  1641
21 General Purpose Timer Array (GPTA ® V5)

1654
- GPTA ® V5 Overview
  1656
- Functionality of GPTA0
  1657
- Functionality of LTCA2
  1659
- GPTA0 Kernel Description
  1660
- GTPA Units
  1661
- Clock Generation Cells
  1662
- Filter and Prescaler Cell (FPC)
  1664
- Phase Discrimination Logic (PDL)
  1673
- Duty Cycle Measurement Cell (DCM)
  1678
- Digital Phase Locked Loop Cell (PLL)
  1682
- Clock Distribution Cell (CDC)
  1687
- Signal Generation Cells
  1690
- Global Timers (GT)
  1690
- Global Timer Cell (GTC)
  1707
- Local Timer Cell (LTC00 to LTC62)
  1719
- Local Timer Cell LTC63
  1731
- Coherent Update
  1737
- Input/Output Line Sharing Block (IOLS)
  1750
- FPC Input Line Selection
  1754
- GTC and LTC Output Multiplexer Selection
  1755
- On-Chip Trigger and Gating Output Multiplexer Selection
  1760
- GTC Input Multiplexer Selection
  1763
- LTC Input Multiplexer Selection
  1768
- Multiplexer Register Array Programming
  1773
- Interrupt Sharing Block (IS)
  1775
- FPC Algorithm
  1778
- PDL-Algorithm
  1783
- DCM-Algorithm
  1787
- PLL-Algorithm
  1790
- GT-Algorithm
  1792
- GTC-Algorithm
  1793
  - LTC-Algorithm for Cells 0 to 62
    1798
  - LTC Algorithm for Cell 63
    1806
- GPTA0 Kernel Registers
  1812
  - Gpta
    1818
  - GPTA ® V5 Identification Register
    1818
- FPC Registers
  1819
- Phase Discriminator Registers
  1823
- Duty Cycle Measurement Registers
  1825
- Digital Phase Locked Loop Registers
  1828
- Global Timer Registers
  1832
- Clock Bus Register
  1834
- Global Timer Cell Registers
  1836
- LTCA Kernel Description
  1881
- Local Timer Cell (LTC00 to LTC63)
  1882
- Output Multiplexer
  1884
- LTC Input Multiplexing Scheme
  1889
- Multiplexer Register Array Programming
  1892
- Interrupt Sharing Block (IS)
  1895
- LTCA Kernel Registers
  1897
  - Bit Protection
    1898
  - I/O Sharing Block Registers
    1910
- LTC Input Multiplexer Control Registers
  1917
- GPTA ® V5 Module Implementation
  1921
- Interconnections of GPTA0/LTCA2 Units
  1921
- I/O Port Line Assignment
  1923
- Port Control and Connections
  1923
- Input/Output Function Selection
  1925
  - Emergency Control of GPTA
    1927
- Clock Bus Connections
  1929
- MSC Controller Connections
  1929
- On-Chip Connections
  1929
- Connections to SCU, Multican, FADC, DMA, Ports
  1935
- Clock Control Registers
  1940
- Fractional Divider Register
  1941
- Limits of Cascading Gtcs and Ltcs
  1945
- Interrupt Registers
  1946
- GPTA Register Address Map
  1947
22 Micro Link Interface (MLI)

1950
- Functional Description
  1951
- General Introduction
  1951
- MLI Overview
  1951
- Naming Conventions
  1953
- MLI Communication Principles
  1955
- MLI Frame Structure
  1959
- General Frame Layout
  1960
- Copy Base Address Frame
  1961
- Write Offset and Data Frame
  1962
- Optimized Write Frame
  1963
- Discrete Read Frame
  1964
- Optimized Read Frame
  1965
- Command Frame
  1966
- Answer Frame
  1967
- Handshake Description
  1968
- Handshake Signals
  1970
- Error-Free Handshake
  1970
- Ready Delay Time
  1971
- Non-Acknowledge Error
  1972
- Signal Timing
  1973
- Parity Generation
  1975
- Address Prediction
  1975
- Module Kernel Description
  1976
- Frame Handling
  1976
- Copy Base Address Frame
  1977
- Write/Data Frames
  1979
- Read Frames
  1983
- Answer Frame
  1988
- Command Frame
  1990
- General MLI Features
  1993
- Parity Check and Parity Error Indication
  1993
- Non-Acknowledge Error
  1996
- Address Prediction
  1996
- Automatic Data Mode
  1997
- Memory Access Protection
  1998
- Triggered Command Transfers
  1998
- Transmit Priority
  2000
- Transmission Delay
  2000
- Interface Description
  2001
- Transmitter I/O Line Control
  2003
- Receiver I/O Line Control
  2003
- Connecting Several MLI Modules
  2005
- MLI Service Request Generation
  2007
- Transmitter Events
  2009
- Parity/Time-Out Error Event
  2010
- Normal Frame Sent X Event
  2010
- Command Frame Sent Events
  2011
- Receiver Events
  2012
- Discarded Read Answer Event
  2012
- Memory Access Protection/Parity Error Event
  2013
- Normal Frame Received/Move Engine Terminated Event
  2014
- Interrupt Command Frame Event
  2015
- Command Frame Received Event
  2016
- Baud Rate Generation
  2017
- Automatic Register Overwrite
  2018
- Operating the MLI
  2019
- Connection Setup
  2020
- Local Transmitter and Pipe Setup
  2021
- Remote Receiver Setup
  2021
- Remote Transmitter and Local Receiver Setup
  2022
- Delay Adjustment
  2023
- Connection to DMA Mechanism
  2025
- Connection of MLI to SPI
  2025
- MLI Kernel Registers
  2027
- General Module Registers
  2030
- General Status/Control Registers
  2034
- Access Protection Registers
  2041
- Transmitter Control/Status Registers
  2044
- Transmitter Pipe X Address Offset Register
  2055
- Transmitter Interrupt Registers
  2059
- Receiver Control/Status Registers
  2065
- Receiver Address/Data Registers
  2069
- Receiver Interrupt Registers
  2072
- Implementation of the MLI0 in TC1784
  2079
  - MLI Module External Registers
    2081
    
    Module Clock Generation
    2082
    
    Port Control and Connections
    2084
    
    On-Chip Connections
    2086
- Break Signals
  2087
- Access Protection
  2087
  - MLI Module External Registers
    2091
    
    Module Clock Generation
    2092
    
    Port Control and Connections
    2094
    
    On-Chip Connections
    2097
- Break Signals
  2098
- Access Protection
  2098
- MLI0/MLI1 Transfer Window Address Maps
  2099
- MLI0 Address Map
  2100
23 Analog to Digital Converter (ADC)

2107
- Introduction
  2107
- ADC Block Diagram
  2108
- Feature Set
  2109
- Abbreviations
  2110
- ADC Kernel Overview
  2111
- Conversion Request Unit
  2113
- Conversion Result Unit
  2115
- Interrupt Structure
  2116
- Electrical Models
  2117
- Input Signal Path
  2117
- Reference Path
  2118
- Transfer Characteristics and Error Definitions
  2120
- Operating the ADC
  2121
- Register Overview
  2122
- Mode Control
  2127
- Module Activation and Power Saving Modes
  2129
  - Clocking Scheme
    2130
  - ADC Module Registers
    2131
    
    Kernel State Configuration Register
    2132
  - General ADC Kernel Registers
    2135
    
    Request Source Input Registers
    2135
    
    Module Identification Register
    2138
    
    Interrupt Activation Register
    2139
    
    Global Control
    2140
    
    Global Configuration
    2143
    
    Global Status
    2145
  - Request Source Arbiter
    2148
    
    Request Source Priority
    2149
    
    Conversion Start Modes
    2150
  - Arbiter Registers
    2153
    
    Arbitration Slot Enable Register
    2153
    
    Request Source Priority Register
    2154
  - Scan Request Source Handling
    2156
    
    Overview
    2156
    
    Scan Sequence Operation
    2157
    
    Request Source Event and Interrupt
    2158
- Scan Request Source Registers
  2160
  - Conversion Request Control Registers
    2160
  - Conversion Request Pending Registers
    2162
  - Conversion Request Mode Registers
    2163
- Sequential Request Source Handling
  2166
  - Overview
    2167
  - Sequential Source Operation
    2168
  - Request Source Event and Interrupt
    2169
- Sequential Source Registers
  2171
  - Queue Mode Registers
    2171
  - Queue Status Registers
    2174
  - Queue 0 Registers
    2176
  - Queue Backup Registers
    2178
  - Queue Input Registers
    2180
- Channel-Related Functions
  2182
  - Input Classes
    2182
  - Reference Selection
    2183
  - Alias Feature
    2183
  - Limit Checking
    2184
  - Channel Event Interrupts
    2186
- Channel-Related Registers
  2187
- Channel Control Registers
  2187
- Input Class Registers
  2189
- Alias Register
  2190
- Limit Check Boundary Registers
  2191
- Channel Flag Register
  2192
- Channel Flag Clear Register
  2193
- Channel Event Node Pointer Registers
  2194
- Conversion Result Handling
  2196
- Storage of Conversion Results
  2196
- Wait-For-Read Mode
  2198
- Result Event Interrupts
  2199
- Result FIFO Buffer
  2200
- Data Reduction Filter
  2202
- Conversion Result-Related Registers
  2204
- Result Registers 1 to 15
  2206
- Valid Flag Register
  2208
- Result Control Registers
  2209
- Event Flag Register
  2211
- Event Flag Clear Register
  2213
- Event Node Pointer Registers
  2214
- Multiplexer Test Support
  2217
- Synchronized Conversions for Parallel Sampling
  2221
- Equidistant Sampling
  2224
- Access Protection
  2226
- Broken Wire Detection
  2227
- Additional Feature Registers
  2229
- Access Protection Register
  2229
- Synchronization Control Register
  2234
- Broken Wire Detection Enable Register
  2236
- Broken Wire Detection Configuration Register
  2237
- Implementation
  2238
- Request Sources in TC1784
  2238
- Address Map
  2238
- ADC Module Connections
  2239
- ADC0 Connections
  2240
- ADC1 Connections
  2246
- Service Request Connections
  2252
- Kernel Synchronization
  2253
24 Fast Analog to Digital Converter (FADC)

2254
- FADC Short Description
  2255
- FADC Kernel Description
  2258
- Analog Input Stage Configurations
  2258
- Result Representation
  2260
- Conversion Timing
  2260
- Channel Triggers
  2261
- Channel Timer
  2262
- Conversion Control
  2265
- Static Channel Priority
  2265
- Dynamic Priority Assignment
  2265
- Clock Generation
  2266
- Suspend Mode Behavior
  2266
- Alias Feature
  2267
- Data Reduction Unit
  2268
- Filter Block Structure
  2269
- Filter Block Operation
  2269
- Filter Concatenation
  2270
- Width of Result Registers
  2272
- Neighbor Channel Trigger
  2273
- Calibration
  2274
- Offset Calibration
  2275
- Interrupt Generation
  2276
- FADC Register Description
  2279
- System Registers
  2283
- Fractional Divider Register
  2284
- Module Identification Register
  2286
- Global Registers
  2288
- Conversion Request Status Register
  2288
- Flag Modification Register
  2290
- Neighbor Channel Trigger Register
  2292
- Global Control Register
  2295
- Alias Register
  2299
- Channel Registers
  2301
- Channel Configuration Registers
  2301
- Analog Control Registers
  2305
- Conversion Result Registers
  2307
- Filter Registers
  2308
- Filter Control Registers
  2308
- Current Result Registers
  2311
- Intermediate Result Registers
  2313
- Final Result Registers
  2315
- Implementation of FADC
  2317
  - Register Overview
    2317
  - Interfaces of the FADC Module
    2318
  - FADC Connections
    2319
  - Service Request Connections
    2320
    
    Clock Control
    2322
    
    User´s Manual L-27 V1.1
    2349

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Motherboard Microcontrollers Computer Hardware Controller Amplifier

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Infineon Technologies TC1784 Manuals

Infineon Technologies TC1784 User Manual (2350 pages)

Table of Contents

1 Introduction

2 CPU Subsystem

3 System Control Unit (SCU)

4 On-Chip System Buses and Bus Bridges

5 Program Memory Unit (PMU)

6 Data Access Overlay (OVC)

7 Bootrom Content

8 Memory Maps

9 General Purpose I/O Ports and Peripheral I/O Lines (Ports)

10 Peripheral Control Processor (PCP)

11 Direct Memory Access Controller (DMA)

12 LMB External Bus Unit

13 Interrupt System

14 System Timer (STM)

15 On-Chip Debug Support (OCDS)

16 Asynchronous/Synchronous Serial Interface (ASC)

17 Synchronous Serial Interface (SSC)

18 Micro Second Channel (MSC)

19 Controller Area Network Controller (Multican)

20 Flexray™ Protocol Controller (E-Ray)

21 General Purpose Timer Array (GPTA ® V5)

22 Micro Link Interface (MLI)

23 Analog to Digital Converter (ADC)

24 Fast Analog to Digital Converter (FADC)

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