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As a special feature, each SLSOn output signal can be combined (ANDed) by an
external signal SLSOANDIn coming from another SSC to an output signal SLSANDOn.
This AND gate can be used for example to combine two slave select output signals from
two SSCs to one common SLSOn output signal. Note that this functionality only works
for low active SLSOn signals (SSOC.AOLn = 0).
Slave Select Output 7 Delayed Mode
In the SLSO7 delayed mode (SSOTC.SLSO7MOD = 1), the timing of the slave select
output SLSO7 as programmed by the three parameters in SSOTC (number of trailing,
leading, and inactive delay clock cycles) is delayed by one shift clock period for the
inactive-to-active edge. The active-to-inactive edge is not delayed. The timing of SLSO7
in the delayed mode is shown in
in normal operating mode, and the dotted lines show the timing of SLSO7 in delayed
mode.
SCLK
SLSO7 with
LEAD = 11
SLSO7 with
LEAD = 10
SLSO7 with
LEAD = 01
SLSO7 with
LEAD = 00
Note: The timing is valid for clock polarity control bit CON.PO = 1
Figure 18-11 SLSO7 Delayed Mode
Slave Select Register Update
At the start of an internal transmit sequence (with the TB register write operation), the
parameters in registers SSOC and SSOTC are latched. This means that they remain
stable while a serial transmission is in progress. Therefore, it is always guaranteed that
the data of one serial transmission is always transmitted with a constant slave select
configuration setup. A configuration change by reprogramming SSOC or SSOTC during
a serial transmission will first become valid with the start of the subsequent serial
transmission.
User's Manual
SSC, V1.41 2010-06
Figure
18-11. The bold lines show the timing of SLSO7
B
B
B
B
Synchronous Serial Interface (SSC)
t
SLSOACT
Data Frame
18-19
TC1728
MCT06222
V1.0, 2011-12
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