Infineon Technologies TC1728 User Manual page 1262

Field Bits
DSDIS 15
NBC [21:16]
PPD [28:24]
0 [23:22],
[31:29]
Note: The "rw" bits in the DSC register are buffered in a shadow buffer at the start of a
corresponding frame transmission.
User's Manual
MSC, V1.37 2009-05
Type Description
rh Downstream Disable
This bit indicates the state of the downstream channel
operation.
0 The downstream channel is enabled. A frame
B
transmission can take place (Triggered Mode) or
takes place (Data Repetition Mode).
1 Downstream Counter becomes disabled. No new
B
frame transmission is started. A running frame
transmission is always completed.
rw Number of Bits Shifted at Command Frames
This bit field determines how many bits of the SRL/SRH
shift registers are shifted out during transmission of a
command frame.
000000 No bit shifted
B
000001 SRL[0] shifted
B
000010 SRL[1:0] shifted
B
000011 SRL[2:0] shifted
B
... ...
B
010000 SRL[15:0] shifted
B
010001 SRL[15:0] and SRH[0] shifted
B
010010 SRL[15:0] and SRH[1:0] shifted
B
... ...
B
011111 SRL[15:0] and SRH[14:0] shifted
B
100000 SRL[15:0] and SRH[15:0] shifted
B
Other bit combinations are reserved; do not use these bit
combinations
rw Passive Phase Length at Data Frames
This bit field determines the length of the passive phase
of a data frame.
Passive phase length is 2 ×
00000
B
Passive phase length is 2 ×
00001
B
Passive phase length is 2 ×
00010
B
Passive phase length is 3 ×
00011
B
... ...
B
Passive phase length is 31 ×
11111
B
r Reserved
Read as 0; should be written with 0.
19-43
Micro Second Channel (MSC)
t
FCL
t
FCL
t
FCL
t
FCL
t
FCL
TC1728
V1.0, 2011-12