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20.3.9.2 Pending Messages
When a message interrupt request is generated, a message pending bit is set in one of
the Message Pending Registers. There are 8 Message Pending Registers, MSPNDk
(k = 0-7) with 32 pending bits available each. The general
allocation of the message pending bits in case that the maximum possible number of
eight Message Pending Registers are implemented and available on the chip.
Message Object n Interrupt Pointer Register MOIPRn[15:0]
MPN
7
6
5
4
3
2 1
15
3
2 1
31
MPSEL
Modul Control Register MCR[31:0]
Figure 20-17 Message Pending Bit Allocation
User's Manual
MultiCAN, V2.24
Controller Area Network Controller (MultiCAN)
TXINP
RXINP
0
3
2
1
0
3
2
0 1
0 1
0 1
1
D
0
7
E
2
6
M
1
5
U
0
1
X
0
1
0
31
D
1
MSB
E
4
0
M
U
X
4
3:0
0
20-40
1
0
0
0 = Transmit Event
0 1
1 = Receive Event
Message Pending Registers
7
255
223
191
159
127
95
63
MSPND1
0
MSPND0
31
. . . . . . . . . . . . . . .
0
0
TC1728
Figure 20-17
shows the
MSPND7
MSPND6
MSPND5
128
MSPND4
96
MSPND3
64
MSPND2
32
0
MCA06274
V1.0, 2011-12
224
192
160
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