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n=0-7. The start address of the block can be an integer multiple of the programmed block
size (natural page boundary).
If the data segment address is A
is compared with the target base addresses of all overlay blocks which are enabled in
RABRx. This bit-wise comparison is qualified by the content of the mask, ignoring the
address bits that form the offset into the overlaid block.
If there is no match, the original data address is taken to perform the access.
If there is a match (see
•
The four segment address bits (A
•
The most significant part of the segment offset, that addresses the base address of
the overlay memory, is set to predefined values according to the address map (fixed
bits in registers RABRx).
•
The part of the target block address, that corresponds to the overlay block base
address, is replaced by the respective overlay block base address bits (bits OBASE
in RABRx, where the corresponding mask bits OMASK in registers OMASKx are set
to "1").
•
The address is completed by the original offset into the block; the number of bits used
are determined by the bits set to "0" in the mask OMASK.
6.2
Online Data Acquisition (OLDA) and its Overlay
Calibration is additionally supported by an OLDA memory range of up to 32 Kbyte, which
is a virtual memory and physically only available, if it is redirected (as described above)
to the internal or external overlay memory or to the EMEM in Emulation Device. If OLDA
is enabled in PMU, direct write accesses (without redirection) to the OLDA range are not
really executed, and they do not generate a bus error trap. This trap suppression works
only for accesses to the non-cached range. Read accesses to the OLDA range generate
a bus error trap, if not redirected to a physically available overlay block.
The base address of the virtual OLDA memory range is A/8FE7 0000
is A/8FE7 7FFF
Accesses to the OLDA range are also supported in cached address
H.
space but there the bus error trap for write accesses is not suppressed.
Note: In OTARx registers, any target address can be selected for redirection, thus also
addresses in the OLDA range. However, the handling of direct accesses to the
OLDA range is completely controlled in the PMU.
6.3
Enable Control of Overlay Blocks
For basic control of overlay execution, the OCON register is provided with following
functionality:
•
16 enable bits (SHOVENx), one for every overlay block configuration, to support
concurrent and parallel switching of up to 16 overlay ranges (blocks); shadow
User's Manual
OVC, V1.20, 2009-07
or 8
, the segment offset of the original data address
H
H
Figure
6-2):
or 8
H
Data Access Overlay (OVC)
) are taken directly from the data address.
H
6-4
TC1728
, the end address
H
V1.0, 2011-12
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