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Calculation of the bit time:
t
= (BRP + 1) /
q
= 8 × (BRP + 1) /
= 1 ×
t
T
Sync
q
= (TSEG1 + 1) ×
T
Seg1
= (TSEG2 + 1) ×
T
Seg2
bit time = T
+ T
Sync
To compensate phase shifts between clocks of different CAN controllers, the CAN
controller must synchronize on any edge from the recessive to the dominant bus level.
If the hard synchronization is enabled (at the start of frame), the bit time is restarted at
the synchronization segment. Otherwise, the re-synchronization jump width T
the maximum number of time quanta, a bit time may be shortened or lengthened by one
re-synchronization. The value of SJW is defined by bit field NBTRx.SJW.
= (SJW + 1) ×
T
SJW
≥ T
T
+ T
Seg1
SJW
≥ T
T
Seg2
SJW
The maximum relative tolerance for
the re-synchronization jump width.
≤ min (T
d
f
CAN
b1
≤ T
/ 20 × bit time
f
d
CAN
SJW
A valid CAN bit timing must be written to the CAN Node Bit Timing Register NBTR before
resetting the INIT bit in the Node Control Register, i.e. before enabling the operation of
the CAN node.
The Node Bit Timing Register may be written only if bit CCE (Configuration Change
Enable) is set in the corresponding Node Control Register.
20.3.5.2 Bitstream Processor
Based on the message objects in the message buffer, the Bitstream Processor
generates the remote and Data Frames to be transmitted via the CAN bus. It controls the
CRC generator and adds the checksum information to the new remote or Data Frame.
After including the SOF bit and the EOF field, the Bitstream Processor starts the CAN
User's Manual
MultiCAN, V2.24
Controller Area Network Controller (MultiCAN)
f
CAN
f
CAN
t
q
t
q
+ T
Seg1
Seg2
t
q
prop
f
CAN
) / 2 × (13 × bit time - T
, T
b2
if DIV8 = 0
if DIV8 = 1
t
(min. 3
)
q
t
(min. 2
)
q
t
(min. 8
)
q
depends on the Phase Buffer Segments and
)
AND
b2
20-23
TC1728
defines
SJW
V1.0, 2011-12
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