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17
Asynchronous/Synchronous Serial Interface (ASC)
This chapter describes the two ASC Asynchronous/Synchronous Serial Interfaces,
ASC0 and ASC1, of the TC1728. It contains the following sections:
•
Functional description of the ASC kernel, valid for ASC0 and ASC1
(see
Page
17-1)
•
ASC kernel register description, describes all ASC kernel specific registers
(see
Page
17-21)
•
TC1728 implementation-specific details and registers of the ASC0/ASC1 modules
(see
Page
17-32).
Note: The ASC kernel register names described in
TC1728 User's Manual by the module name prefix "ASC0_" for the ASC0 interface
and by "ASC1_" for the ASC1 interface.
17.1
ASC Kernel Description
Figure 17-1
shows a global view of the ASC interface.
Clock
Control
Address
Decoder
Interrupt
Control
To DMA
Figure 17-1 General Block Diagram of the ASC Interface
The ASC module communicates with the external world via two I/O lines. The RXD line
is the receive data input signal (and also output signal in Synchronous Mode), and TXD
is the transmit output signal.
Clock control, address decoding, and interrupt service request control are managed
outside the ASC module kernel.
User's Manual
ASC, V1.3 2007-11
Asynchronous/Synchronous Serial Interface (ASC)
f
ASC
ASC
Module
(Kernel)
EIR
TBIR
TIR
RIR
Section 17.2
RXD
Port
Control
TXD
17-1
TC1728
are referenced in the
RXD
TXD
MCB05762_mod
V1.0, 2011-12
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