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clock, changes between one cycle before and two cycles after the latching edge of the
shift clock signal SCLK. This condition sets the error status flag STAT.PE and, if enabled
via CON.PEN, the error interrupt request line EIR.
Note: When CON.PH = 1, the data output signal may be disturbed shortly when the
slave select input signal is changed after a serial transmission, resulting in a phase
error.
A Baud Rate Error (Slave Mode) is detected when the incoming clock signal deviates
from the programmed baud rate (shift clock) by more than 100%, meaning it is either
more than double or less than half the expected baud rate. This condition sets the error
status flag STAT.BE and, if enabled via CON.BEN, the EIR line. Using this error
detection capability requires that the slave's shift clock generator is programmed to the
same baud rate as the master device. This feature detects false additional pulses or
missing pulses on the clock line (within a certain frame).
Note: If this error condition occurs and bit CON.AREN = 1, an automatic reset of the
SSC will be performed. This is done to re-initialize the SSC, if too few or too many
clock pulses have been detected.
Note: The baud rate error can occur in slave mode after any transfer if the
communication is stopped by the master. This is the case due to the fact that SSC
module supports back-to-back transfers for multiple transfers. In order to handle
this the baud rate detection logic expects after a finished transfer immediately a
next clock cycle for a new transfer.
If baud rate error is enabled and the transmit buffer of the slave SSC is loaded with a
new value for the next data frame while the current data frame is not yet finished (while
STAT.BSY = 1), the slave SSC expects continuation of the clock pulses for the next data
frame transmission immediately after finishing the current data frame. Any write to TBUF
of the slave SSC while STAT.BSY = 1 initiates or sustains a continuous transmission in
the slave. Therefore, the master (shift) clock must be continued after the current frame
transmission. Otherwise, the slave SSC will detect a baud rate error. Note that the
master SSC does not necessarily send out a continuous shift clock in the case that its
transmit buffer is not yet filled with new data or transmission delays occur. Further details
on continuous transfers are described in
A Transmit Error (Slave Mode) is detected when a transfer was initiated by the master
(shift clock gets active), but the transmit buffer (TB) of the slave was not updated since
the last transfer. If enabled via CON.TEN, this condition sets the error status flag
STAT.TE and activates the EIR line. This condition sets the error status flag STAT.TE
and, if enabled via CON.TEN, the EIR line. If a transfer starts while the transmit buffer is
not updated, the slave will shift out the 'old' contents of the shift register, which is
normally the data received during the last transfer. This may lead to the corruption of the
data on the transmit/receive line in half-duplex mode (open drain configuration) if this
slave is not selected for transmission. This mode requires that slaves not selected for
User's Manual
SSC, V1.41 2010-06
Synchronous Serial Interface (SSC)
Section 18.1.2.4
on
18-22
TC1728
Page
18-10.
V1.0, 2011-12
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