Table of Contents
Advertisement
TC1728
Synchronous Serial Interface (SSC)
18.1.2
General Operation
The SSC supports full-duplex and half-duplex synchronous communication up to
55.0 Mbit/s (@ 110.0 MHz module clock). The serial clock signal can be generated by
the SSC itself (Master Mode) or be received from an external master (Slave Mode). Data
width, shift direction, clock polarity and phase are programmable. This allows
communication with SPI-compatible devices. Transmission and reception of data are
double-buffered. A shift clock generator provides the SSC with a separate serial clock
signal.
Configuration of the high-speed synchronous serial interface is very flexible, so it can
work with other synchronous serial interfaces, can serve master/slave or multi-master
interconnections, or can operate compatibly with the popular SPI interface. It can be
used to communicate with shift registers (I/O expansion), peripherals (e.g. EEPROMs
etc.), or other controllers (networking). The SSC supports half-duplex and full-duplex
communication. Data is transmitted or received on pins MTSR (Master Transmit/Slave
Receive) and MRST (Master Receive/Slave Transmit). The clock signal is output or input
via pin SCLK (Serial Clock). These three pins are typically used for alternate output
functions of port pins. If they are implemented as dedicated bi-directional pins, they can
be directly controlled by the SSC. In Slave Mode, the SSC can be selected from a master
via dedicated slave select input lines (SLSI). In Master Mode, automatic generation of
slave select output lines (SLSO) is supported. In Master Mode, control and data handling
of transfers can be also be controlled independently by the DMA controller (Queued SSC
Mode).
User's Manual
18-3
V1.0, 2011-12
SSC, V1.41 2010-06
Advertisement
Table of Contents
