Peripheral Monitoring Selection - Infineon Technologies TC1728 User Manual

15.4.10

Peripheral Monitoring Selection

The Table 15-4 shows the list of peripherals present in the TC1728 device together with
an identifier. The FPI bus infrastructure provides address decoders that are configured
to generate chip select signals. The chip select signals are connected to the standard
BPI modules or to the FPI Slave Interfaces or directly to custom FPI interfaces (some
FPI peripherals have neither a BPI nor a FPI slave interface). Each select line identifies
a FPI region that corresponds to the FPI regions defined in the
registers. Behind a decoded FPI region there may be multiple peripherals. This situation
is reflected in Table
will all use the DMA identifier. Only the FPI write transactions enabled by
PSET1 will be stored in the BMU.
Table 15-4 Identification of FPI Regions
Unit
System Peripheral Bus Control Unit (SBCU)
System Timer (STM)
System Control Unit (SCU) and Watchdog Timer (WDT)
MicroSecond Bus Controller 0 (MSC0)
Async./Sync. Serial Interface 0 (ASC0)
Async./Sync. Serial Interface 1 (ASC1)
Port Group 0
Port Group 1
Port Group 2
General Purpose Timer Array (GPTA0)
Capture/Compare Unit 6 0 (CCU60)
Capture/Compare Unit 6 1 (CCU61)
General Purpose Timer 12 0 (GPT120)
General Purpose Timer 12 1 (GPT121)
Direct Memory Access Controller (DMA)
On-Chip Debug Support (Cerberus)
Micro Link Interface 0 (MLI0)
Memory Checker (MCHK)
User's Manual
BMU, V2.6
15-4. Peripherals that belong to the DMA subsystem (FPI extension)
FPI Region Identifier
0
1
2
3
5
5
6
7
8
10
11
11
13
14
16
17
Belongs to DMA region 2
17
Belongs to DMA region 2
17
Belongs to DMA region 2
15-22
TC1728
Bus Monitor Unit (BMU)
PSET0 and PSET1
PSET0
V1.0, 2011-12
and