Infineon Technologies TC1728 User Manual page 1189

Field Bits
HB 4
PH 5
PO 6
LB 7
TEN 8
REN 9
PEN 10
BEN 11
AREN 12
User's Manual
SSC, V1.41 2010-06
Type Description
rw Heading Bit Control
0 Transmit/Receive LSB First
B
1 Transmit/Receive MSB First
B
rw Clock Phase Control
0 Shift transmit data on the leading clock edge,
B
latch on trailing edge
1 Latch receive data on leading clock edge, shift
B
on trailing edge
rw Clock Polarity Control
0 Idle clock line is low, the leading clock edge is
B
low-to-high transition
1 Idle clock line is high, the leading clock edge is
B
high-to-low transition
rw Loop-Back Control
0 Normal output
B
1 Receive input is connected to transmit output
B
(Half-duplex Mode)
rw Transmit Error Enable
0 Ignore transmit errors
B
1 Check transmit errors
B
rw Receive Error Enable
0 Ignore receive errors
B
1 Check receive errors
B
rw Phase Error Enable
0 Ignore phase errors
B
1 Check phase errors
B
rw Baud Rate Error Enable
0 Ignore baud rate errors
B
1 Check baud rate errors
B
rw Automatic Reset Enable
0 No additional action upon a baud rate error
B
1 SSC is automatically reset on a baud rate error
B
18-32
Synchronous Serial Interface (SSC)
TC1728
V1.0, 2011-12