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Field
Bits
CLRBE
11
SETTE
12
SETRE
13
SETPE
14
SETBE
15
0
[3:1],
[7:5],
[31:16]
Note: When the set and clear bits for an error flag are set at the same time during an
EFM write operation (e.g SETPE = CLRPE = 1), the error flag in STAT is not
affected.
User's Manual
SSC, V1.41 2010-06
Type Description
w
Clear Baud Rate Error Flag
0
No effect
B
1
Bit STAT.BE is cleared.
B
Bit is always read as 0.
w
Set Transmit Error Flag
0
No effect
B
1
Bit STAT.TE is set.
B
Bit is always read as 0.
w
Set Receive Error Flag
0
No effect
B
1
Bit STAT.RE is set.
B
Bit is always read as 0.
w
Set Phase Error Flag
0
No effect
B
1
Bit STAT.PE is set.
B
Bit is always read as 0.
w
Set Baud Rate Error Flag
0
No effect
B
1
Bit STAT.BE is set.
B
Bit is always read as 0.
r
Reserved
Read as 0; should be written with 0.
18-37
Synchronous Serial Interface (SSC)
TC1728
V1.0, 2011-12
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