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17.1.1
Overview
The ASC provides serial communication between the TC1728 and other
microcontrollers, microprocessors, or external peripherals.
The ASC supports full-duplex asynchronous communication and half-duplex
synchronous communication. In Synchronous Mode, data is transmitted or received
synchronous to a shift clock that is generated by the ASC internally. In Asynchronous
Mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be
selected. Parity, framing, and overrun error detection are provided to increase the
reliability of data transfers. Transmission and reception of data is double-buffered. For
multiprocessor communication, a mechanism is included to distinguish address bytes
from data bytes. Testing is supported by a loop-back option. A 13-bit baud rate generator
provides the ASC with a separate serial clock signal, which can be accurately adjusted
by a prescaler implemented as fractional divider.
Features
•
Full-duplex asynchronous operating modes
– 8-bit or 9-bit data frames, LSB first
– Parity-bit generation/checking
– One or two stop bits
– Baud rate from 6.875 Mbit/s to 1.64 bit/s (@ 110 MHz module clock)
– Multiprocessor mode for automatic address/data byte detection
– Loop-back capability
•
Half-duplex 8-bit synchronous operating mode
– Baud rate from 13.75 Mbit/s to 1119 bit/s (@ 110 MHz module clock)
•
Double-buffered transmitter/receiver
•
Interrupt generation
– On a transmit buffer empty condition
– On a transmit last bit of a frame condition
– On a receive buffer full condition
– On an error condition (frame, parity, overrun error)
•
Implementation features
– Connections to DMA Controller
– Connections of receiver input to GPTA (LTC) for baud rate detection and LIN break
signal measuring
User's Manual
ASC, V1.3 2007-11
Asynchronous/Synchronous Serial Interface (ASC)
17-2
TC1728
V1.0, 2011-12
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