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17.1.3.2 Asynchronous Transmission
Asynchronous transmission begins when the next overflow of the divide-by-16 baud rate
timer (transition of the baud rate clock
loaded into TBUF. The transmitted data frame consists of three elements:
1. The start bit
2. The data field (8 or 9 bits, LSB first, including a parity bit, if selected)
3. The delimiter (1 or 2 stop bits)
Data transmission is double-buffered. When the transmitter is idle, the transmit data
loaded into TBUF is immediately moved to the transmit shift register; thus, freeing TBUF
for the next transmit data to be loaded. This is indicated by the transmit buffer interrupt
request line TBIR being activated. TBUF may then be loaded with the next transmit data
while transmission of the previous one continues.
The Transmit Interrupt Request line TIR will be activated before the last bit of a frame is
transmitted, that is, before the first or the second stop bit is shifted out of the transmit
shift register.
Note: A dedicated GPIO device pin which is connected to the module output pin TXD
must be configured by software as alternate data output for asynchronous
transmission.
17.1.3.3 Asynchronous Reception
Asynchronous reception is initiated by a falling edge (1-to-0 transition) on pin RXD, on
the condition that bits CON.R and CON.REN are set. The receive data input pin RXD is
sampled at sixteen times the rate of the selected baud rate. A majority decision of the
th
th
th
7
, 8
and 9
sample determines the effective sampled bit value. This avoids erroneous
results that may be caused by noise.
If the detected value is not a 0 when the start bit is sampled, the receive circuit is reset
and waits for the next 1-to-0 transition at pin RXD. If the start bit proves valid, the receive
circuit continues sampling and shifts the incoming data frame into the receive shift
register.
When the last stop bit has been received, the contents of the receive shift register are
transferred to the Receive Data Buffer Register RBUF. Simultaneously, the receive
interrupt request line RIR is activated after the 9
programmed), regardless whether valid stop bits have been received or not. The receive
circuit then waits for the next start bit (1-to-0 transition) at the receive data input line.
Note: A dedicated GPIO pin that is connected to the module input pin RXD must be
configured by software as input for asynchronous reception.
Asynchronous reception is stopped by clearing bit CON.REN. A currently received frame
is completed including generation of the receive interrupt request and an error interrupt
request, if appropriate. Start bits that follow this frame will not be recognized.
User's Manual
ASC, V1.3 2007-11
Asynchronous/Synchronous Serial Interface (ASC)
f
) occurs, if bit CON.R is set and data has been
BR
th
sample in the last stop bit time-slot (as
17-7
TC1728
V1.0, 2011-12
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