Infineon Technologies TC1728 User Manual page 1128

Using the Fractional Divider
When the fractional divider is selected, the input clock
derived from the module clock
CON.FDE = 1, the fractional divider is activated. It divides
any value of n from 0 to 511. If n = 0, the divider ratio is 1, which means that
In general, the fractional divider allows the baud rate to be programmed with much better
accuracy than with the two fixed prescaler divider stages.
Note: In fractional divider mode, the clock
f clock period.
ASC
Table 17-3 Asynchronous Baud Rate Formulas using the Fractional Input Clock
Divider
FDE BRS
1 –
BG represents the content of the reload register bit field BG.BR_VALUE, taken as an
unsigned 13-bit integer. FDV represents the contents of the fractional divider register bit
field FDV.FD_VALUE, taken as an unsigned 9-bit integer.
Table 17-4 Typical Asynchronous Baud Rates using the Fractional Input Clock
Divider
f
Desired
ASC
Baud Rate
110 MHz 115.2 kbit/s
57.6 kbit/s
User's Manual
ASC, V1.3 2007-11
Asynchronous/Synchronous Serial Interface (ASC)
f
ASC
BG FDV
0 ... 8191 1 ... 511
0
BG FDV
003A 1FA
H
0075 1FA
H
17-16
f
DIV
by a programmable fractional divider. If
f
ASC
f can have a maximum period jitter of one
DIV
Formula
FDV
----------- -
Baud rate =
512
Baud rate
Resulting
Baud Rate
115.160 kbit/s
H
57.579 kbit/s
H
TC1728
for the baud rate timer is
by a fraction of n/512 for
f
DIV
f
×
ASC
----------------------------------- -
× (
16 BG + 1
f
ASC
= ----------------------------------- -
× ( )
16 BG + 1
Deviation
-0.04%
-0.04%
V1.0, 2011-12
f
= .
ASC
)