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to DMA etc.
STM
IR0
Interrupt
STM
Control
IR1
Enable /
Disable
Clock
f
STM
Control
Address
Decoder
Application Reset
Figure 14-1 General Block Diagram of the STM Module Registers
User's Manual
STM, V1.6
31
STM_CMP0
Compare Register 0
STM_CMP1
55
47
00
H
00
H
STM_TIM5
STM_TIM4
STM_TIM3
STM_TIM2
STM_TIM1
14-3
23
15
7
31
23
Compare Register 1
39
31
23
56-bit System Timer
STM_CAP
STM_TIM6
STM_TIM0
TC1728
System Timer (STM)
STM Module
0
15
7
0
15
7
MCB06185_mod
V1.0, 2011-12
0
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