Clock Control Register - Infineon Technologies TC1728 User Manual

19.3.3.1 Clock Control Register

The Clock Control Register allows the programmer to control (enable/disable) the clock
signals to the MSC0 module under certain conditions. The diagram below shows the
clock control register functionality as is implemented for the MSC0 module.
MSC0_CLC
MSC0 Clock Control Register
31 30 29 28
15 14 13 12
Field Bits
DISR 0
DISS 1
SPEN 2
EDIS 3
SBWE 4
FSOE 5
0 [31:6]
Note: After a hardware reset operation, the
the MSC0 module is disabled (DISS set).
User's Manual
MSC, V1.37 2009-05
(00
27 26 25 24
11 10 9 8
0
r
Type Description
rw Module Disable Request Bit
Used for enable/disable control of the module.
r Module Disable Status Bit
Bit indicates the current status of the module.
rw Module Suspend Enable for OCDS
Used to enable the suspend mode
rw Sleep Mode Enable Control
Used to control module's sleep mode.
w Module Suspend Bit Write Enable for OCDS
Determines whether SPEN and FSOE are write-
protected.
rw Fast Switch Off Enable
Used to switch off fast clock in Suspend Mode.
r Reserved
Read as 0; should be written with 0.
19-67
Micro Second Channel (MSC)
) Reset Value: 0000 0003
H
23 22 21
0
r
7 6 5
FS SB
OE WE
rw
f f
and clocks are switched off and
CLC0 MSC0
TC1728
20 19 18 17
4 3 2 1
E SP DIS
DIS EN S
w rw rw r
V1.0, 2011-12
H
16
0
DIS
R
rw