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16.3
Debug Interface (Cerberus)
The Cerberus module is the on-chip unit that controls all OCDS main debug functions.
Generally, the Cerberus may not be used by any application software, since this could
disturb the emulation tool behavior.
The Cerberus module is built up by three parts (see also
•
OCDS System Control Unit - OSCU
•
IOClient
•
Multi Core Break Switch - MCBS
A tool can be connected to the device in two ways:
•
A two line DAP interface via the DAP module receives the debugger commands,
converts them and outputs them to the IOClient interface.
•
Standard JTAG interface is connected via the JTAG controller with the IOClient
interface
Two additional pins are available to handle an external break condition. The external
debug hardware can access the Cerberus registers and arbitrary memory locations
across the System Peripheral Bus.
Features
•
OCDS Level 1 control via
– 5-pin standard JTAG interface
– 2-pin DAP interface
•
Generation of external break condition via BRKIN/BRKOUT pins possible
•
Full access to the complete SPB Bus address space via DAP/JTAG
•
No user resources (hardware/software) are required
•
No or minimum run-time impact (Cerberus bus priority can be controlled)
•
Generic memory read/write functionality
•
Write word, half-word and byte
•
Block read and write
•
Full support for communication between an on-chip monitor program and the
external debugger
•
Pending reads/writes can be optionally triggered by the OCDS module (memory
tracing)
•
Download of programs and data via DAP/JTAG
•
Control of the OCDS blocks
•
Data acquisition
16.3.1
RW Mode
As the name implies, the RW mode is used by a DAP/JTAG host to read or write arbitrary
memory locations via the DAP/JTAG interface. The RW mode needs the SPB Bus
master interface of the Cerberus to actively request data reads or data writes.
User's Manual
OCDS, V1.5
On-Chip Debug Support (OCDS)
Figure
16-10
TC1728
16-1):
V1.0, 2011-12
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