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13.3
Interrupt Control Units
The Interrupt Control Units manage the interrupt system, arbitrate incoming service
requests, and determine whether and when to interrupt the service provider. The
TC1728 contains two interrupt control units, one for the CPU (called ICU), and one for
the PCP (called PICU). Each one controls its associated interrupt arbitration bus and
manages the communication with its service provider (see ).
13.3.1
Interrupt Control Unit (ICU)
This section describes the interrupt control unit (ICU) for the CPU.
13.3.1.1 ICU Interrupt Control Register (ICR)
The ICU Interrupt Control Register ICR holds the current CPU priority number (CCPN),
the global interrupt enable/disable bit (IE), the pending interrupt priority number (PIPN),
and bit fields which control the interrupt arbitration process.
ICR
ICU Interrupt Control Register
31
30
29
28
0
r
15
14
13
12
Field
Bits
CCPN
[7:0]
User's Manual
Interrupt, V1.4
(F7E1FE2C
27
26
25
C
ONE
CARBCYC
CYC
rw
11
10
9
0
r
Type Description
rwh
Current CPU Priority Number
The Current CPU Priority Number (CCPN) bit field
indicates the current priority level of the CPU. It is
automatically updated by hardware on entry and exit of
interrupt service routines, and through the execution of
a BISR instruction. CCPN can also be updated through
an MTCR instruction.
)
H
24
23
22
rw
8
7
6
IE
rwh
13-8
Interrupt System
Reset Value: 0000 0000
21
20
19
18
PIPN
rh
5
4
3
2
CCPN
rwh
TC1728
H
17
16
1
0
V1.0, 2011-12
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