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TC1728
Interrupt System
to process the observation. During this second phase, it may be acceptable for this ISR
to be interrupted by lower-level interrupts. This can be performed as follows.
For example, the initial interrupt priority is fixed very high because response time is
critical. The necessary actions are carried out immediately by the ISR at that high-priority
level. Then the ISR prepares to invoke another ISR at a lower priority level through
software to perform the lower-priority actions.
To invoke an ISR through software, the high-priority ISR directly sets an interrupt request
bit in an SRN that will invoke the appropriate low-priority ISR. Then the high-priority ISR
exits.
When the high-priority ISR exits, the pending low-priority interrupt will eventually be
serviced (depending on the priority of other pending interrupts). When the low-priority
ISR eventually executes, the low-priority actions of the interrupt will be performed.
The inverse of this method can also be employed, wherein a low-priority ISR raises its
own priority level, or leaves interrupts turned off while it executes. For instance, the
priority of a service request might be low because the time to respond to the event is not
critical, but once it has been granted service, this service should not be interrupted. In
this case, the ISR could raise the value of ICR.CCPN to a priority that would exclude
some or all other interrupts, or simply leave interrupts disabled.
13.8.5
Using different Priorities for the same Interrupt Source
For some applications, the urgency of a service request may vary, depending on the
current state of the system. To handle this, different priority numbers (SRPNs) can be
assigned at different times to a service request depending on the application needs.
Of course, Interrupt Service Routines must be placed in the Interrupt Vector Table at all
addresses corresponding to the range of priorities used. If service remains the same at
different priorities, copies of the ISR can be placed at the possible different entries, or
the entries can all vector to a common ISR. If the ISR should execute different code
depending on its priority, one need merely put the appropriate ISR in the appropriate
entry of the Interrupt Vector Table.
This flexibility is another advantage of the TC1728 interrupt architecture. In traditional
interrupt systems where the interrupt vectors are ordered by interrupting source, the ISR
would have to check the current priority of the interrupt request and perform a branch to
the appropriate code section, causing a delay in the response to the request. In the
TC1728, however, the extra check and branch in the ISR are not necessary, hence
reduces the interrupt latency.
Because this approach may necessitate an increase in the range of interrupt priorities,
the system designer must trade off this advantage against any possible increase in the
number of arbitration cycles.
User's Manual
13-21
V1.0, 2011-12
Interrupt, V1.4
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