Baud Rate; Abort Of Frames - Infineon Technologies TC1728 User Manual

When the selection bit for the SRL active frame is disabled (ENSELL = 0, see
Figure 19-13), the loading of the shift register SRL/SRH (and reset of the downstream
counter) occurs one FCL clock cycle before the first data bit SRL.0 is output. ENL is set
to high level with the beginning of the first data bit SRL.0.
SRL/SRH
Loading
State of
DSS.DC
FCL
SO
ENL
ENH
Figure 19-13 Shift Clock Counting: Data Frame with ENSELL = 0 and ENSELH = 0

19.1.2.5 Baud Rate

The baud rate of the downstream channel's serial transmission is defined by the
frequency of the serial clock FCL, and is always
specific and depends on the implementation of the MSC module. The TC1728 specific
clock generation is described on

19.1.2.6 Abort of Frames

Only a reset condition of the device can abort a current transmission. The MSC module
does not start a new frame transmission when the downstream channel becomes
disabled, the suspend mode is requested, or the sleep mode is entered. If one of these
three conditions becomes active during a running frame transmission, the frame
transmission is completely finished before the requested abort state is entered. Note that
in this case no time frame finished interrupt is generated any more.
User's Manual
MSC, V1.37 2009-05
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