Infineon Technologies TC1728 User Manual page 1196

The Slave Select Output Timing Control Register controls the operation of the Slave
Select Output Generation Unit.
SSOTC
Slave Select Output Timing Control Register
31 30 29 28
15 14 13 12
QSM
EN
EN
rw w
Field Bits
LEAD [1:0]
TRAIL [3:2]
User's Manual
SSC, V1.41 2010-06
(1C
27 26 25 24
11 10 9 8
SLS
0 O7
MOD
r rw
Type Description
rw Slave Output Select Leading Delay
This bit field determines the number of leading delay
clock cycles. A leading delay clock cycle is always a
multiple of an SCLK shift clock period.
00 Zero leading delay clock cycle selected
B
01 One leading delay clock cycle selected
B
10 Two leading delay clock cycles selected
B
11 Three leading delay clock cycles selected
B
rw Slave Output Select Trailing Delay
This bit field determines the number of trailing delay
clock cycles. A trailing delay clock cycle is always a
multiple of an SCLK shift clock period.
00 Zero trailing delay clock cycle selected
B
01 One trailing delay clock cycle selected
B
10 Two trailing delay clock cycles selected
B
11 Three trailing delay clock cycles selected
B
18-39
Synchronous Serial Interface (SSC)
) Reset Value: 0000 0000
H
23 22 21
0
r
7 6 5
0 INACT
r rw
TC1728
20 19 18 17
4 3 2 1
TRAIL LEAD
rw
1)
1)
V1.0, 2011-12
H
16
0
rw