Infineon Technologies TC1728 User Manual page 1190

Field Bits
MS 14
EN 15
PARTEN 16
PARREN 17
PARTYP 18
PAREEN 19
User's Manual
SSC, V1.41 2010-06
Type Description
rw Master Select
0 Slave Mode. Operate on shift clock received via
B
SCLK
1 Master Mode. Generate shift clock and output it
B
via SCLK
The inverted state of this bit is available on module
output line "M/S selected" (see
rw Enable Bit
0 Transmission and reception are disabled.
B
1 Transmission and reception are enabled.
B
This bit is available as module output line "SSC
enabled" (see
be cleared by software while no transfer is in progress
(STAT.BSY = 0). Note that the transmission/reception
enable can also be controlled in queued SSC mode by
bit SSOTC.EN (see
rw Parity Transmit Enable Bit
This bit enables the parity mode for the transmission of
frames.
0 Parity mode for transmission is disabled.
B
1 Parity mode for transmission is enabled.
B
rw Parity Receive Enable Bit
This bit enables the parity mode for the reception of
frames.
0 Parity mode for reception is disabled.
B
1 Parity mode for reception is enabled.
B
rw Parity Type Bit
If PAREN = 1, this bit defines the type of parity to be
generated or checked.
0 Even parity is selected (parity bit = 1 on odd
B
number of 1s in data, parity bit = 0 on even
number of 1s in data).
1 Odd parity selected (parity bit = 1 on even
B
number of 1s in data, parity bit = 0 on odd
number of 1s in data)
rw Parity Error Enable
0 Ignore receive parity errors
B
1 Check receive parity errors
B
18-33
Synchronous Serial Interface (SSC)
Figure
Figure 18-2). Note that EN should only
Page 18-24).
TC1728
18-2).
V1.0, 2011-12